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| cypress semiconductor corporation 198 champion court san jose , ca 95134 - 1709 408 - 943 - 2600 document number: 002 - 14826 rev. *b revised july 1, 2016 the following document contains information on cypress products. although the document is marked with the name broadcom , the company that originally developed the specification, cypress will continue to offer these pr oducts to new and existing customers. continuity of specifications there is no change to this document as a result of offering the device as a cypress product. any changes that have been made are the result of normal document improvements and are noted in the document history page, where supported. future revisions will occur when appropriate, and changes will be noted in a document history page. continuity of ordering part numbers cypress continues to support existing part numbers. to order these products , please use only the ordering part numbers listed in this document. for more information please visit our website at www .cypress.com or contact your local sales office for additional information about cypress pro ducts and services. our customers cypress is for true innovators C in companies both large and small. our customers are smart, aggressive, out - of - the - box thinkers who design and develop game - changing products that revolutionize their industries or create n ew industries with products and solutions that nobody ever thought of before. about cypress founded in 1982, cypress is the leader in advanced embedded system solutions for the worlds most innovative automotive, industrial, home automation and appliances, consumer electronics and medical products. cypresss programmable systems - on - chip, general - purpose microcontrollers, analog ics, wireless and usb - based connectivity solutions and reliable, high - performance memories help engineers design differentiated pro ducts and get them to market first. cypress is committed to providing customers with the best support and engineering resources on the planet enabling innovators and out - of - the - box thinkers to disrupt markets and create new product categories in record tim e. to learn more, go to www.cypress.com .
43903-ds102-r corporate headquarters: san jose, ca march 12, 2016 preliminary data sheet BCM43903 wiced ? ieee 802.11 b/g/n soc with an embedded applications processor general description features the broadcom ? ltd. BCM43903 embedded wireless system-on-a-chip (soc) is uniquely suited for internet-of-things applications. it supports all rates specified in the ieee 802.11 b/g/n specifications.the device includes an arm cortex-based applications processor, a single stream ieee 802.11n mac/ baseband/radio, a power amplifier (pa), and a receive low-noise amplifier (lna). it also supports optional antenna diversity for improved rf performance in difficult environments. the BCM43903 is an optimized soc targeting embedded internet-of-things applications in the industrial and medical sensor, and home appliance markets. using advanced design techniques and process technology to reduce active and idle power, the device is designed for embedded applications that require minimal power consumption and a compact size. the device includes a pmu for simplifying system power topology and allows for direct operation from a battery while maximizing battery life. features application processor features ? arm cortex-r4 32-bit risc processor. ? 1 mb of on-chip sram for code and data. ? an on-chip cryptography core ? 640 kb of rom containing wiced sdk components such as rtos and tcp/ip stack. ? 17 gpios supported. ? q-spi serial flash interface to support up to 40 mbps of peak transfer. ? support for uart (3), spi or bsc master, and bsc-only interfaces. (broadcom serial control (bsc) is an i 2 c-compatible interface.) key ieee 801.11x features ? ieee 802.11n compliant. ? single-stream spatial multiplexing up to 150 mbps. ? supports 20 mhz channels with optional sgi. ? full ieee 802.11 b/g legacy compatibility with enhanced performance. ? tx and rx low-density parity check (ldpc) support for improved range and power efficiency. ? on-chip power and low-noise amplifiers. ? an internal fractional npll allows support for a wide range of reference clock frequencies. ? integrated arm cortex-r4 processor with tightly coupled memory for complete wlan subsystem functionality, minimizing the need to wake up the applications processor for standard wlan functions (to further minimize power consumption while maintaining the ability to upgrade to future features in the field). ? software architecture supported by standard wiced sdk allows easy migration from existing discrete mcu designs and to future devices. ? security support: ? wpa and wpa2 (personal) support for powerful encryption and authentication. ? aes and tkip in hardware for faster data encryption and ieee 802.11i compatibility. ? reference wlan subsystem provides cisco compatible extensions (ccx, ccx 2.0, ccx 3.0, ccx 4.0, and ccx 5.0). ? wi-fi protected setup and wi-fi easy-setup ? worldwide regulatory support: global products supported with worldwide design approval. general features ? supports battery voltage range from 3.0v to 4.8v with an internal switching regulator. ? programmable dynamic power management. ? 6 kb otp memory for storing board parameters. ? 151-ball wlbga (4.91mm x 5.85mm, 0.4mm pitch) revision history BCM43903 preliminary data sheet broadcom ? march 12, 2016 ? 43903-ds102-r page 2 broadcom confidential figure 1: functional block diagram BCM43903 apps domain wlan always-on domain uart dma 32 kb (i), 32 kb (d) icache axi to axi bridge crytography engine apps arm cortex-r4 1 mb ram, 640 kb rom spi pwm (6) bsc gpio (17) 32 khz external lpo rtc ps ram ps sr_eng pmu control pmu axi-to-axi bridge axi vio vbat reg_on hib_reg_on_in axi ieee 802.11 mac 1 x 1, ieee 802.11n phy 2.4 ghz radio lna 2.4 ghz axi-to-axi bridge wlan arm cortex-r4 tcm 512 kb ram 320 kb rom axi pa rf switch controls 37.4 mhz crystal bsc = broadcom serial control. an i 2 c-compatible interface. spi or bsc tx switch tx switch wrf_rfin_2g wrf_paout_2g bsc pwm spi gpio jtag ? 2016 by broadcom. all rights reserved. broadcom ? , the pulse logo, connecting everything ? , the connecting everything logo, and avago technologies are among the trademarks of broadcom and/or its affiliates in the united states, certain other countries and/or the eu. any other trademarks or trade names mentioned are the property of their respective owners. broadcom reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. information furnished by broadcom is believed to be accurate and reliable. however, broadcom does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. this data sheet (including, without limitation, the broadcom component(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous substances management, or other high-risk application. broadcom provides this data sheet ?as-is,? without warranty of any kind. broadcom disclaims all warranties, expressed and implied, including, without limitation, the implied warranties of merchantability, fitnes s for a particular purpose, and non- infringement. revision history revision date change description 43903-ds102-r 03/12/16 updated: ? general edits 43903-ds101-r 11/03/15 updated: ? table 21: ?absolute maximum ratings,? on page 109. ? table 24: ?recommended operating conditions and dc characteristics,? on page 111 ? table 30: ?wlan 2.4 ghz receiver performance specifications,? on page 116 ? table 31: ?wlan 2.4 ghz transmitter performance specifications,? on page 119. 43903-ds100-r 10/15/2015 initial release table of contents BCM43903 preliminary data sheet broadcom ? march 12, 2016 ? 43903-ds102-r page 4 broadcom confidential table of contents about this document ............................................................................................................................... .10 purpose and audience ........................................................................................................... ............... 10 acronyms and abbreviations..................................................................................................... ............ 10 document conventions ........................................................................................................... .............. 10 technical support ............................................................................................................................... ....... 10 section 1: overview .......................................................................................................... 11 introduction ............................................................................................................................... .................. 11 features ....................................................................................................................... ......................... 12 standards compliance ............................................................................................................................... 12 section 2: power supplies and power management ..................................................... 14 power supply topology ............................................................................................................................. 14 BCM43903 power management unit features ......................................................................................... 14 power management ............................................................................................................................... ..... 16 pmu sequencing ............................................................................................................................... ......... 18 power-off shutdown ............................................................................................................................... ... 19 power-up/power-down/reset circuits ..................................................................................................... 19 section 3: frequency references.................................................................................... 20 crystal interface and clock generation ................................................................................................... 20 external frequency reference .................................................................................................................. 21 frequency selection ............................................................................................................................... ... 22 external 32.768 khz low-power oscillator .............................................................................................. 23 section 4: applications subsystem................................................................................. 24 overview ............................................................................................................................... ....................... 24 applications cpu and memory subsystem ............................................................................................. 24 memory-to-memory dma core .................................................................................................................. 24 cryptography core ............................................................................................................................... ...... 25 section 5: applications subsystem external interfaces ............................................... 26 gpio ............................................................................................................................... .............................. 26 broadcom serial control ........................................................................................................................... 26 jtag and arm serial wire debug ............................................................................................................ 26 pwm ............................................................................................................................... .............................. 27 real-time clock ............................................................................................................................... ........... 27 spi flash ............................................................................................................................... ...................... 28 uart ............................................................................................................................... ............................. 28 table of contents BCM43903 preliminary data sheet broadcom ? march 12, 2016 ? 43903-ds102-r page 5 broadcom confidential section 6: global functions ............................................................................................ 29 external coexistence interface ................................................................................................................. 29 one-time programmable memory ............................................................................................................ 29 hibernation block ............................................................................................................................... ........ 30 system boot sequence .............................................................................................................................. 3 0 section 7: wireless lan subsystem ............................................................................... 31 wlan cpu and memory subsystem ........................................................................................................ 31 ieee 802.11n mac ............................................................................................................................... ....... 31 psm............................................................................................................................ ........................... 33 wep ............................................................................................................................ .......................... 33 txe ............................................................................................................................ ........................... 34 rxe ............................................................................................................................ ........................... 34 ifs............................................................................................................................ ............................. 34 tsf............................................................................................................................ ............................ 35 nav ............................................................................................................................ ........................... 35 mac-phy interface.............................................................................................................. ................. 35 ieee 802.11 ? b/g/n phy ............................................................................................................................ 36 section 8: wlan radio subsystem ............................................................................... 38 receiver path ............................................................................................................................... ............... 38 transmit path ............................................................................................................................... ............... 38 calibration ............................................................................................................................... .................... 38 section 9: pinout and signal descriptions ..................................................................... 40 ball map ............................................................................................................................... ........................ 40 ball list ............................................................................................................................... ......................... 41 signal descriptions ............................................................................................................................... ..... 44 section 10: gpio signals and strapping options.......................................................... 49 overview ............................................................................................................................... ....................... 49 weak pull-down and pull-up resistances ............................................................................................... 49 strapping options ............................................................................................................................... ....... 50 alternate gpio signal functions .............................................................................................................. 51 section 11: pin multiplexing............................................................................................. 52 section 12: i/o states........................................................................................................ 5 4 section 13: electrical characteristics ............................................................................. 57 absolute maximum ratings ...................................................................................................................... 57 environmental ratings .............................................................................................................................. 5 8 electrostatic discharge specifications .................................................................................................... 58 recommended operating conditions and dc characteristics ............................................................. 59 table of contents BCM43903 preliminary data sheet broadcom ? march 12, 2016 ? 43903-ds102-r page 6 broadcom confidential power supply segments ............................................................................................................................ 61 gpio, uart, and jtag interfaces dc characteristics .......................................................................... 61 section 14: wlan rf specifications .............................................................................. 62 introduction ............................................................................................................................... .................. 62 2.4 ghz band general rf specifications ................................................................................................. 62 wlan 2.4 ghz receiver performance specifications ............................................................................ 63 wlan 2.4 ghz transmitter performance specifications ....................................................................... 66 general spurious emissions specifications ........................................................................................... 67 transmitter spurious emissions specifications .................................................................................. .. 67 2.4 ghz band spurious emissions ................................................................................................ 67 20-mhz channel spacing ...................................................................................................... 67 receiver spurious emissions specifications ..................................................................................... ... 68 section 15: internal regulator electrical specifications ............................................... 69 core buck switching regulator ................................................................................................................ 69 3.3v ldo (ldo3p3) ............................................................................................................................... ..... 70 cldo ............................................................................................................................... ............................ 71 lnldo ............................................................................................................................... .......................... 72 bbpll ldo ............................................................................................................................... .................. 73 section 16: system power consumption........................................................................ 74 wlan current consumption ..................................................................................................................... 74 2.4 ghz mode ................................................................................................................... .................... 74 section 17: spi flash characteristics ............................................................................. 76 spi flash timing ............................................................................................................................... .......... 76 read-register timing ........................................................................................................... ................ 76 write-register timing.......................................................................................................... .................. 77 memory fast-read timing........................................................................................................ ............ 78 memory-write timing ............................................................................................................ ................ 79 spi flash parameters ........................................................................................................... ................ 80 section 18: power-up sequence and timing ................................................................. 81 sequencing of reset and regulator control signals ............................................................................. 81 description of control signals ................................................................................................. .............. 81 control signal timing diagrams................................................................................................. ........... 82 section 19: thermal information...................................................................................... 83 package thermal characteristics ............................................................................................................. 83 junction temperature estimation and psi jt versus theta jc ............................................................. 83 environmental characteristics .................................................................................................................. 83 table of contents BCM43903 preliminary data sheet broadcom ? march 12, 2016 ? 43903-ds102-r page 7 broadcom confidential section 20: mechanical information ................................................................................ 84 section 21: ordering information .................................................................................... 85 list of figures BCM43903 preliminary data sheet broadcom ? march 12, 2016 ? 43903-ds102-r page 8 broadcom confidential list of figures figure 1: functional block diagram.............................................................................................. ..................... 2 figure 2: block diagram and i/o................................................................................................. ..................... 11 figure 3: typical power topology (page 1 of 2).................................................................................. ............ 15 figure 4: typical power topology (page 2 of 2).................................................................................. ............ 16 figure 5: recommended oscillator configuration .................................................................................. ......... 20 figure 6: recommended circuit to use with an external reference clock .................................................... 21 figure 7: broadcom 2-wire external coexistence interface ........................................................................ .... 29 figure 8: wlan mac architecture ................................................................................................. ................. 32 figure 9: wlan phy block diagram................................................................................................ ............... 37 figure 10: radio functional block diagram ....................................................................................... ............. 39 figure 11: 151-ball wlbga map?top view with balls facing down ........................................................... 40 figure 12: port locations for wlan testing ...................................................................................... ............. 62 figure 13: spi flash read-register timing ....................................................................................... ............. 76 figure 14: spi flash write-register timing ...................................................................................... .............. 77 figure 15: memory fast-read timing .............................................................................................. ............... 78 figure 16: memory-write timing .................................................................................................. ................... 79 figure 17: spi flash timing parameters diagram .................................................................................. ........ 80 figure 18: reg_on = high, no hib_reg_on_out connection to reg_on ............................................. 82 figure 19: hib_reg_on_in = high, hib_reg_on_out connected to reg_on ...................................... 82 figure 20: wlbga package ........................................................................................................ .................... 84 list of tables BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 9 list of tables table 1: BCM43903 power modes ................................................................................................... ............... 17 table 2: power-up/power-down/reset control signals.............................................................................. .... 19 table 3: crystal oscillator and external clock?requirements and performance ......................................... 21 table 4: external 32.768 khz sleep clock specifications ......................................................................... ...... 23 table 5: jtag_sel and tap_sel states for test and debug function selection........................................ 27 table 6: wlbga net names ........................................................................................................ ................... 41 table 7: signal descriptions .................................................................................................... ........................ 44 table 8: strapping options ...................................................................................................... ........................ 50 table 9: alternate gpio signal functions ........................................................................................ ............... 51 table 10: pin multiplexing...................................................................................................... .......................... 52 table 11: i/o states ............................................................................................................ ............................. 54 table 12: absolute maximum ratings .............................................................................................. ............... 57 table 13: environmental ratings ................................................................................................. .................... 58 table 14: esd specifications .................................................................................................... ...................... 58 table 15: recommended operating conditions and dc characteristics ........................................................ 59 table 16: power supply segments................................................................................................. ................. 61 table 17: gpio, uart, and jtag interfaces ....................................................................................... .......... 61 table 18: 2.4 ghz band general rf specifications................................................................................ ........ 62 table 19: wlan 2.4 ghz receiver performance specifications .................................................................... 63 table 20: wlan 2.4 ghz transmitter performance specifications ................................................................ 66 table 21: recommended spectrum analyzer settings ................................................................................ ... 67 table 22: 2.4 ghz band, 20-mhz channel spacing tx spurious emissions specifications ......................... 68 table 23: 2g general receiver spurious emissions................................................................................ ....... 68 table 24: core buck switching regulator (cbuck) specifications ................................................................ 69 table 25: ldo3p3 specifications ................................................................................................. ................... 70 table 26: cldo specifications ................................................................................................... ..................... 71 table 27: lnldo specifications .................................................................................................. .................... 72 table 28: bbpll ldo specifications .............................................................................................. ................ 73 table 29: 2.4 ghz mode wlan current consumption ................................................................................. .. 74 table 30: spi flash timing parameters ........................................................................................... ............... 80 table 31: package thermal characteristics ....................................................................................... ............. 83 about this document broadcom ? march 12, 2016 ? 43903-ds102-r page 10 BCM43903 preliminary data sheet broadcom confidential about this document purpose and audience this document provides details of the functional, operational, and electrical characteristics of the broadcom ? ltd. BCM43903. it is intended for hardware design, application, and oem engineers. acronyms and abbreviations in most cases, acronyms and abbreviations are defined on first use. for a comprehensive list of acronyms and other terms used in broadcom documents, go to: http://www.broadcom.com/press/glossary.php . document conventions the following conventions may be used in this document: technical support broadcom provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, pcb layout information, and software updates through its customer support portal ( https://support.broadcom.com ). for a csp account, contact your sales or engineering support representative. in addition, broadcom provides other product support through its downloads and support site ( http://www.broadcom.com/support/ ). convention description bold user input and actions: for example, type exit , click ok , press alt+c monospace code: #include command line commands and parameters: wl [-l] |
overview BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 11 section 1: overview introduction the broadcom ltd. BCM43903 is a single-chip device that provides the highest level of integration for an embedded system-on-a-chip with integrated ieee 802.11 b/g/n mac/baseband/radio and a separate arm cortex-r4 applications processor. it provides a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for an embedded system with flexibility in size, form, and function. comprehensive power management circuitry and software ensure that the system can meet the needs of highly embedded systems that require minimal power consumption and reliable operation. figure 2 shows the interconnect of all the major physical blocks in the BCM43903 and their associated external interfaces, which are described in greater detail in section 5: ?applications subsystem external interfaces,? on page 26 . figure 2: block diagram and i/o note: another spi interface can be defined by reconfiguring gpio_8 through gpio_11 and another bsc interface can be defined by reconfiguring gpio_12 and gpio_13 (see table 10: ?pin multiplexing,? on page 52 ). apps subsystem wlan subsystem BCM43903 spi flash gpio[16:0] 2x 2-wire uart 4-wire uart spi/bsc bsc jtag/swd wake rf tx rf rx switch control antenna diversity vddios gnd arm cortex-r4 320 mhz 32 kb i-cache 32 kb d-cache 1 mb sram 640 kb rom arm cortex-r4 160 mhz 448 kb rom tcm 576 kb sram tcm 802.11n 1x1 2.4 ghz standards compliance BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 12 features the BCM43903 supports the following features: ? arm cortex-r4 clocked at 160 mhz (in 1 mode) or up to 320 mhz (in 2 mode). ? 1 mb of sram and 640 kb rom available for the applications processor. ? one high-speed 4-wire uart interface with operation up to 4 mbps. ? two low-speed 2-wire uart interfaces multiplexed on general purpose i/o (gpio) pins. ? one dedicated bsc 1 interface. ? one spi master/slave interface with operation up to 24 mhz. ? one spi master interface for serial flash. ? six dedicated pwm outputs. ? 17 gpios. ? ieee 802.11 b/g/n 11 2.4 ghz radio. ? single- and dual-antenna support. standards compliance the BCM43903 supports the following standards: ? ieee 802.11n ? ieee 802.11b ? ieee 802.11g ? ieee 802.11d ? ieee 802.11h ? ieee 802.11i ? security: ?wep ? wpa personal ? wpa2 personal 1. broadcom serial control (bsc) is an i 2 c-compatible interface. note: another bsc interface can be defined by reconfiguring gpios. see table 10: ?pin multiplexing,? on page 52 . note: in addition to the dedicated bsc interface, the spi interface can be used as a bsc master interface. note: another spi interface can be defined by reconfiguring gpios. see table 10: ?pin multiplexing,? on page 52 . standards compliance BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 13 ?wmm ? wmm-ps (u-apsd) ?wmm-sa ? aes (hardware accelerator) ? tkip (hardware accelerator) ? ckip (software support) ? proprietary protocols: ? ccxv2 ? ccxv3 ? ccxv4 ? ccxv5 ?wfaec the BCM43903 supports the following additional standards: ? ieee 802.11r?fast roaming (between aps) ? ieee 802.11w?secure management frames ? ieee 802.11 extensions: ? ieee 802.11e qos enhancements (already supported as per the wmm specification) ? ieee 802.11i mac enhancements ? ieee 802.11k radio resource measurement power supplies and power management BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 14 section 2: power supplies and power management power supply topology one core buck regulator, multiple ldo regulators, and a power management unit (pmu) are integrated into the BCM43903. all regulators are programmable via the pmu. these blocks simplify power supply design for application and wlan functions in embedded designs. a single vbat (3.0v to 4.8v dc maximum) and vio supply (1.8v to 3.3v) can be used, with all additional voltages being provided by the regulators in the BCM43903. the reg_on control signal is used to power up the regulators and take the appropriate sections out of reset. the cbuck, cldo, lnldo, and other regulators power up when any of the reset signals are deasserted. all regulators are powered down only when reg_on is deasserted. the regulators may be turned off/on based on the dynamic demands of the digital baseband. the BCM43903 provides a low power-consumption mode whereby the cbuck, cldo, and lnldo regulators are shut down. when in this state, the low-power linear regulator (lpldo1) supplied by the system vio supply provides the BCM43903 with all required voltages. BCM43903 power management unit features the BCM43903 supports the following power management unit (pmu) features: ? vbat to 1.35vout (550 ma maximum) core buck (cbuck) switching regulator ? vbat to 3.3vout (450 ma maximum) ldo3p3 ? 1.35v to 1.2vout (350 ma maximum) cldo with bypass mode for deep-sleep ? 1.35v to 1.2vout (55 ma maximum) ldo for bbpll ? additional internal ldos (not externally accessible) ? pmu internal timer auto-calibration by the crystal clock for precise wake-up timing from the low power- consumption mode. figure 3 and figure 4 on page 16 show the regulators and a typical power topology. broadcom ? march 12, 2016 ? 43903-ds102-r page 15 BCM43903 power management unit features broadcom confidential BCM43903 preliminary data sheet figure 3: typical power topology (page 1 of 2) vbat 1.35v BCM43903 1.2v reg_on core buck regulator (cbuck) lpldo1 cldo vddio xtal ldo cap-less lnldo cap-less lnldo cap-less vcoldo cap-less lnldo cap-less lnldo 1.2v apps subcore apps socsram apps vddm wl vddm (srams in aos) wl subcore wl phy wlan/clb/top, always on 1.3v, 1.2v, .095v (avs) wlrf rfpll, pfd, and mmd 1.35v wlrf xtal wlrf adc ref wlrf tx wlrf afe and tia wlrf lna wlrf logen wlrf tx mixer and pa (not always) 1.2v 1.2v 1.2v 1.2v 1.2v mini-pmu (inside wl radio) 15 ma vbat operational: 2.3v to 4.8v performance: 3.0v to 4.8v absolute maximum: 5.5v vddio operational: 3.3v supply ball supply bump/pad ground ball ground bump/pad external to chip power switch no power switch no dedicated power switch, but internal power- down modes and block-specific power switches wlan reset ball bbpll lnldo wl bbpll/dfll 1.2v power management BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 16 figure 4: typical power topology (page 2 of 2) power management the BCM43903 has been designed with the stringent power consumption requirements of mobile devices in mind. all areas of the chip design are optimized to minimize power consumption. silicon processes and cell libraries were chosen to reduce leakage current and supply voltages. additionally, the BCM43903 includes an advanced power management unit (pmu) sequencer. the pmu sequencer provides significant power savings by putting the BCM43903 into various power management states appropriate to the environment and activities that are being performed. the power management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. power-up sequences are fully programmable. configurable, free-running counters (running at a 32.768 khz lpo clock) in the pmu sequencer are used to turn on and turn off individual regulators and power switches. clock speeds are dynamically changed (or gated altogether) as a function of the mode. slower clock speeds are used whenever possible. ta b l e 1 provides descriptions for the BCM43903 power modes. vbat ldo3p3 BCM43903 2.5v and 3.3v wlrf pa wlrf pad vddio_rf wl otp 3.3v 2.5v cap-less lnldo 2.5v cap-less lnldo 2.5v cap-less lnldo inside wl radio 3.3v vcoldo2p5 wl rf rx, tx, nmos, mini-pmu ldos wl rf vco wl rf cp 2.5v 2.5v 450 to 800 ma supply ball supply bump/pad ground ball ground bump/pad external to chip power switch no power switch no dedicated power switch, but internal power- down modes and block-specific power switches power management BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 17 table 1: BCM43903 power modes mode description active all wlan blocks in the BCM43903 are powered up and fully functional with active carrier sensing and frame transmission and receiving. all required regulators are enabled and put in the most efficient mode based on the load current. clock speeds are dynamically adjusted by the pmu sequencer. doze the radio, analog domains, and most of the linear regulators are powered down. the rest of the BCM43903 remains powered up in an idle state. all main clocks (pll, crystal oscillator, or tcxo) are shut down to minimize active power consumption. the 32.768 khz lpo clock is available only for the pmu sequencer. this condition is necessary to allow the pmu sequencer to wake up the chip and transition to active mode. in doze mode, the primary power consumed is due to leakage current. deep-sleep most of the chip, including both analog and digital domains and most of the regulators, is powered off. logic states in the digital core are saved and preserved in a retention memory in the always- on domain before the digital core is powered off. upon a wake-up event triggered by the pmu timers or an external interrupt, logic states in the digital core are restored to their pre-deep- sleep settings to avoid lengthy hw reinitialization. power-down the BCM43903 is effectively powered off by shutting down all internal regulators. the chip is brought out of this mode by external logic re-enabling the internal regulators. pmu sequencing BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 18 pmu sequencing the pmu sequencer minimizes system power consumption. it enables and disables various system resources based on a computation of required resources and a table that describes the relationship between resources and the time required to enable and disable them. resource requests can come from several sources: clock requests from cores, the minimum resources defined in the resourcemin register, and the resources requested by any active resource-request timers. the pmu sequencer maps clock requests into a set of resources required to produce the requested clocks. each resource is in one of the following four states: ? enabled ?disabled ? transition_on ? transition_off the timer contains 0 when the resource is enabled or disabled and a nonzero value when in a transition state. the timer is loaded with the time_on or time_off value of the resource after the pmu determines that the resource must be enabled or disabled and decrements on each 32.768 khz pmu clock. when it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. if the time_on value is 0, the resource can transition immediately from disabled to enabled. similarly, a time_off value of 0 indicates that the resource can transition immediately from enabled to disabled. the terms enable sequence and disable sequence refer to either the immediate transition or the timer load-decrement sequence. during each clock cycle, the pmu sequencer performs the following actions: ? computes the required resource set based on requests and the resource dependency table. ? decrements all timers whose values are nonzero. if a timer reaches 0, the pmu clears the resourcepending bit of the resource and inverts the resourcestate bit. ? compares the request with the current resource status and determines which resources must be enabled or disabled. ? initiates a disable sequence for each resource that is enabled, is no longer being requested, and has no powered-up dependents. ? initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled. power-off shutdown BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 19 power-off shutdown the BCM43903 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other system devices remain operational. when the BCM43903 is not needed in the system, vddio_rf and vddc are shut down while vddio remains powered. this allows the BCM43903 to be effectively off while keeping the i/o pins powered so that they do not draw extra current from devices connected to the i/o. during a low-power shutdown state, provided vddio remains applied to the BCM43903, all outputs are tristated and most inputs signals are disabled. input voltages must remain within the limits defined for normal operation. this is done to prevent current paths or create loading on any digital signals in the system, and enables the BCM43903 to be fully integrated in an embedded device while taking full advantage of the lowest power-saving modes. when the BCM43903 is powered on from this state, it is the same as a normal power-up and does not retain any information about its state from before it was powered down. power-up/power-down/reset circuits the BCM43903 has two signals (see table 2 ) that enable or disable circuits and the internal regulator blocks, allowing the host to control power consumption. for timing diagrams of these signals and the required power- up sequences, see section 18: ?power-up sequence and timing,? on page 81 . table 2: power-up/power-down/reset control signals signal description reg_on this signal is used by the pmu to power up the BCM43903. it controls the internal BCM43903 regulators. when this pin is high, the regulators are enabled and the device is out of reset. when this pin is low, the device is in reset and the regulators are disabled. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. hib_reg_on_in this signal is used by the hibernation block to decide whether or not to power down the internal BCM43903 regulators. if hib_reg_on_in is low, the regulators will be disabled. for a signal at hib_reg_on_in to function as intended, hib_reg_on_out must be connected to reg_on. frequency references BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 20 section 3: frequency references an external crystal is used for generating all radio frequencies and normal-operation clocking. as an alternative, an external frequency reference can be used. in addition, a low-power oscillator (lpo) is provided for lower power mode timing. crystal interface and clock generation the BCM43903 can use an external crystal to provide a frequency reference. the recommended crystal oscillator configuration, including all external components, is shown in figure 5 . consult the reference schematics for the latest configuration. figure 5: recommended os cillator configuration a fractional-n synthesizer in the BCM43903 generates the radio frequencies, clocks, and data/packet timing, enabling it to operate using a wide selection of frequency references. the recommended default frequency reference is a 37.4 mhz crystal. the signal characteristics for the crystal interface are listed in table 3 on page 21 . note: although the fractional-n synthesizer can support alternative reference frequencies, frequencies other than the default require support to be added in the driver, plus additional extensive system testing. contact broadcom for further details. wrf_xtal_xop wrf_xtal_xon c c programmable internal series resistor is from 50 ohms to 500 ohms in steps of 50 ohms. boot-up rom value is 50 ohms. 37.4 mhz x ohms device boundary 27 pf 27 pf programmable internal shunt caps are from 0 pf to 7.5 pf in steps of 0.5 pf. 1.3 pf 0.4 pf external resistor and programmable internal resistor value is determined by crystal drive level. note: a reference schematic is available for further details. contact your broadcom fae. external frequency reference BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 21 external frequency reference as an alternative to a crystal, an external precision frequency reference can be used, provided that it meets the phase noise requirements listed in ta b l e 3 . if used, the external clock should be connected to the wrf_xtal_xon pin through an external 1000 pf coupling capacitor, as shown in figure 6 . the internal clock buffer connected to this pin will be turned off when the BCM43903 goes into sleep mode. when the clock buffer turns on and off, there will be a small impedance variation. power must be supplied to the wrf_xtal_vdd1p35 pin. figure 6: recommended circuit to use with an external reference clock table 3: crystal oscillator and extern al clock?requirements and performance parameter conditions/notes crystal a external frequency reference b c units min. typ. max. min. typ. max. frequency 2.4 ghz band: ieee 802.11n operation and legacy ieee 802.11b/g operation between 19 mhz and 52 mhz d frequency tolerance over the lifetime of the equipment, including temperature e without trimming ?20 ? 20 ?20 ? 20 ppm crystal load capacitance ? ?16????pf esr ? ??60??? ? drive level external crystal must be able to tolerate this drive level. 200?????w input impedance (wrf_xtal_xon) resistive ? ? ? 30k 100k ? ? capacitive ??7.5??7.5pf wrf_xtal_xon input low level dc-coupled digital signal ???0?0.2v wrf_xtal_xon input high level dc-coupled digital signal ???1.0?1.26v wrf_xtal_xon input voltage (see figure 6 ) ieee 802.11b/g operation only ? ? ? 400 ? 1200 mv p-p reference clock nc 1000 pf wrf_xtal_xon wrf_xtal_xop frequency selection BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 22 frequency selection any frequency within the ranges specified for the crystal and tcxo reference may be used. these include not only the standard handset reference frequencies of 19.2, 19.8, 24, 26, 33.6, 37.4, 38.4, and 52 mhz, but also other frequencies in this range, with approximately 80 hz resolution. the BCM43903 must have the reference frequency set correctly in order for any of the external interfaces to function correctly, since all bit timing is derived from the reference frequency. wrf_xtal_xon input voltage (see figure 6 ) ieee 802.11n ac-coupled analog input ???1??v p-p duty cycle 37.4 mhz clock ???405060% phase noise f (ieee 802.11b/g) 37.4 mhz clock at 10 khz offset??????129dbc/hz 37.4 mhz clock at 100 khz offset??????136dbc/hz phase noise f (ieee 802.11n, 2.4 ghz) 37.4 mhz clock at 10 khz offset??????134dbc/hz 37.4 mhz clock at 100 khz offset??????141dbc/hz a. (crystal) use wrf_xtal_xon and wrf_xtal_xop. b. see ?external frequency reference? on page 21 for alternative connection methods. c. for a clock reference other than 37.4 mhz, 20 log10(f/ 37.4) db should be added to the limits, where f = the reference clock frequency in mhz. d. the frequency step size is approximately 80 hz. e. it is the responsibility of the equipment designer to select oscillator components that comply with these specifications. f. assumes that external clock has a flat phase noise response above 100 khz. note: the fractional-n synthesizer can support many reference frequencies. however, frequencies other than the default require support to be added in the driver plus additional, extensive system testing. contact broadcom for more information. table 3: crystal oscillator and external clock?requirements and performance (cont.) parameter conditions/notes crystal a external frequency reference b c units min. typ. max. min. typ. max. external 32.768 khz low-power oscillator BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 23 the reference frequency for the BCM43903 may be set in the following ways: ? set the xtalfreq=xxxxx parameter (in hertz) in the nvram.txt file (used to load the driver) to correctly match the crystal frequency. ? auto-detect any of the standard handset reference frequencies using an external lpo clock. for applications such as handsets and portable smart communication devices, where the reference frequency is one of the standard frequencies commonly used, the BCM43903 automatically detects the reference frequency and programs itself to the correct reference frequency. in order for automatic frequency detection to work correctly, the BCM43903 must have a valid and stable 32.768 khz lpo clock that meets the requirements listed in table 4 on page 23 and is present during a power-on reset. external 32.768 khz low-power oscillator the BCM43903 uses a secondary low frequency clock for low-power-mode timing. either the internal low- precision lpo or an external 32.768 khz precision oscillator is required. the internal lpo frequency range is approximately 33 khz 30% over process, voltage, and temperature, which is adequate for some applications. however, one tradeoff caused by this wide lpo tolerance is a small current consumption increase during power save mode that is incurred by the need to wake-up earlier to avoid missing beacons. whenever possible, the preferred approach is to use a precision external 32.768 khz clock that meets the requirements listed in ta b le 4 . table 4: external 32.768 khz sleep clock specifications parameter lpo clock units nominal input frequency 32.768 khz frequency accuracy 200 ppm duty cycle 30?70 % input signal amplitude 200?3300 mv, p-p signal type square-wave or sine-wave ? input impedance a a. when power is applied or switched off. >100k <5 ? pf clock jitter (during initial start-up) <10,000 ppm applications subsystem BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 24 section 4: applications subsystem overview the applications subsystem contains the general use cpu, memory, the standalone dma core, the cryptography core, and the majority of the external interfaces. applications cpu and memory subsystem this subsystem has an integrated 32-bit arm cortex-r4 processor with an internal 32 kb d-cache and an internal 32 kb i-cache. the arm cortex-r4 is a low-power processor that features a low gate count, low interrupt latency, and low-cost debugging capabilities. it is intended for deeply embedded applications that require fast interrupt response features. the arm cortex-r4 implements the arm v7-r architecture and supports the thumb-2 instruction set. at 0.19 w/mhz, the cortex-r4 is the most power efficient general-purpose microprocessor available, outperforming 8- and 16-bit devices on a mips/w basis. it also supports integrated sleep modes. using multiple technologies to reduce cost, the arm cortex-r4 enables improved memory utilization, reduced pin overhead, and reduced silicon area. it also has extensive debugging features, including real-time tracing of program execution. on-chip memory for the cpu includes 1 mb sram, 640 kb rom, and an 8 kb ram powered independently of the application subsystem. memory-to-memory dma core the BCM43903 memory-to-memory dma (m2mdma) engine contains eight dma channel pairs, each containing one transmit/pull engine and one receive/push engine. the dma engine provides general purpose data movement between memories that can be on the device, attached directly to the device, or accessed through a host interface. the transmit/pull engine reads data from the source memory and immediately passes it to the paired receive/push engine, which proceeds to write it to the destination memory. multiple masters can program the individual channels, and multiple interrupts are provided so that interrupts for different channels can be routed separately to different masters. cryptography core BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 25 cryptography core this core provides general purpose data movement between memories, which may be either on the device, attached directly to the device, or accessed through a host interface. the transmit/pull engine reads data from the source memory and passes it immediately to the paired receive/push engine that proceeds to write it to the destination memory. multiple masters may program the individual channels, and multiple interrupts are provided so that interrupts for different channels can be routed separately to different masters. the cryptography block provides a hardware accelerator for enciphering and deciphering data that has undergone processing using standards-based encryption algorithms. the cryptography block includes the following primary features: ? encryption and hash engines that support single pass auth-enc or enc-auth processing. ? a scalable aes module that supports cbc, ecb, ctr, cfb, ofb, and xts encryption with 128-, 192-, and 256-bit key sizes. ? a scalable des module that supports des and 3des in ecb and cbc modes. ? an rc4 stream cipher module that supports state initialization, state update, and key-stream generation. ? md5, sha1, sha224, and sha256 engines that support pure hash or hmac operations. ? a built-in 512-byte key cache for locally protected key storage. otp memory is used to store authentication keys. applications subsystem external interfaces BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 26 section 5: applications subsystem external interfaces gpio there are 17 general-purpose i/o (gpio) pins available on the BCM43903. the gpios can be used to connect to various external devices. upon power-up and reset, these pins are tristated. subsequently, they can be programmed to be either input or output pins via the gpio control register. in addition, the gpio pins can be assigned to various other functions. apart from other functions, gpios are used to set bootstrap options and use the jtag interface for debugging during software development. broadcom serial control the BCM43903 has two broadcom serial control (bsc 2 ) master interfaces for external communication with codecs, dacs, nvram, etc. the i/o pads can be configured as pull-ups or pull-ups can be installed on the reference design to support a multimaster on an open drain bus. jtag and arm serial wire debug the BCM43903 supports the ieee 1149.1 jtag boundary scan standard for performing device package and pcb assembly testing during manufacturing. in addition, the jtag interface allows broadcom to assist customers by using proprietary debug and characterization test tools during board bring-up. therefore, it is highly recommended to provide access to the jtag pins by means of test points or a header on all pcb designs. the BCM43903 also supports arm serial wire debug (swd) for connecting a jtag debugger directly to both arm cortex-r4s. for swd, the combination of a clock and a bidirectional signal (on a single pin) provides normal jtag debug and test functionality. the reduced pin-count swd interface is a high-performance alternative to the jtag interface. 2. broadcom serial control is an i 2 c compatible interface. pwm BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 27 table 5 shows the jtag_sel and tap_sel states for test and debug function selection. test and debug function selection is independent of the debugging interface (jtag or swd) being used. pwm the BCM43903 provides up to six independent pulse width modulation (pwm) channels. the following features apply to the pwm channels: ? each channel is a square wave generator with a programmable duty cycle. ? each channel generates its duty cycle by dividing down the input clock. ? both the high and low duration of the duty cycle can be divided down independently by a 16-bit divider register. ? each channel can work independently or update simultaneously. ? pairs of pwm outputs can be inverted for devices that need a differential output. ? continuous or single pulses can be generated. ? the input clock can either be a high-speed clock from a pll channel or a lower speed clock at the crystal frequency. real-time clock the BCM43903 provides a real-time clock (rtc) provided that an accurate 32.768 khz crystal is used. the rtc generates date/time using the 32.768 khz reference and is always powered on when the chip is on, except while in hibernation mode. the rtc has a precision of seconds and will display the calendar day and time provided the initial start time is programmed correctly. the second, minute, hour, day, month, year, and 24-hour mode can be set individually. interrupts can be set on any periodic time event or on specific time events. the pmu uses the rtc interrupt to determine when to wake up the chip. table 5: jtag_sel and tap_sel states for test and debug function selection jtag_sel state tap_sel state test and debug function 0 0 jtag not used. 0 1 jtag not used. 1 0 access the lv tap directly for ate and bring-up. 1 1 access either of the arm cortex-r4?s directly via either the 5-pin jtag port or the 2-pin swd configuration. spi flash BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 28 spi flash the spi flash interface supports the following features: ? a spi-compatible serial bus. ? an 80 mhz (maximum) clock frequency. ? quad i/o, which provides increased throughput to 40 mb/s. ? support for either 1 or 4 addresses with 4 data. ? 3-bytes and 4-byte addressing modes. ? a configurable dummy-cycle count that is programmable from 1 to 15. ? programmable instructions output to serial flash. ? an option to change the sampling edge from rising-edge to falling-edge for read-back data when in high- speed mode. uart a high-speed 4-wire cts/rts uart interface can be enabled by software and has dedicated pins. provided primarily for debugging during development, this uart enables the BCM43903 to operate as rs-232 data termination equipment (dte) for exchanging and managing data with other serial devices. it is compatible with the industry standard 16550 uart and provides a fifo size of 64 8 in each direction. there are two low-speed uart interfaces on the BCM43903. each functions as a standard 2-wire uart. they are also enabled as alternate functions on gpios and ca n be enabled independently of the 4-wire fast uart. global functions BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 29 section 6: global functions external coexistence interface an external handshake interface is available to enable signaling between the device and an external colocated wireless device, such as bluetooth, to manage wireless medium sharing for optimum performance. figure 7 shows the coexistence interface. figure 7: broadcom 2-wire external coexistence interface one-time programmable memory various hardware configuration parameters can be stored in an internal 6144-bit (768 bytes) one-time programmable (otp) memory that is read by system software after a device reset. in addition, customer- specific parameters, including the system vendor id and mac address can be stored, depending on the specific board design. the initial state of all bits in an unprogrammed otp memory device is 0. after any bit is programmed to a 1, it cannot be reprogrammed to 0. the entire otp memory array can be programmed in a single write-cycle using a utility provided with the broadcom wlan manufacturing test tools. alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits that are still in the 0 state can be altered during each programming cycle. prior to otp memory programming, all values should be verified using the appropriate editable nvram.txt file. the nvram.txt file is provided with the reference board design package. bt\ic gci wlan uart_in uart_out seci_out ? seci_out/bt_txd and seci_in/bt_rxd are multiplexed on the gpios. ? the 2-wire coexistence interface is intended for future compatibility with the bt sig 2-wire interface that is being standardiz ed for core 4.1. notes: seci_in BCM43903 hibernation block BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 30 hibernation block the hibernation (hib) block is a self-contained power domain that can be used to completely shut down the rest of the BCM43903. this optional block uses the hib_reg_on_out pin to drive the reg_on pin. therefore, for the hib block to work as designed, the hib_reg_on_out pin must be connected to the reg_on pin. to use the hib block, software programs the hib block with a wake count and then asserts a signal indicating that the chip should be put into hibernation. after assertion, the hib block drives hib_reg_on_out low for the number of 32 khz clock cycles programmed as the wake count. after the wake-count timer expires, hib_reg_on_out is driven high. other than the logic state of the hib block, no state is saved in the BCM43903 during hibernation. system boot sequence the following general sequence occurs after a BCM43903 is powered on: 1. either reg_on or hib_reg_on_in is asserted. 2. the core ldo (cldo) and ldo3p3 outputs stabilize. 3. the otp memory bits are used to initialize various functions, such as pmu trimming, package selection, memory size selection, etc. 4. the app and wlan cores are powered up. 5. the xtal is powered up. 6. the app and wlan cpu bootup sequences start. note: for hib_reg_on_in to function as intended, hib_reg_on_out must be connected to reg_on. wireless lan subsystem BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 31 section 7: wireless lan subsystem wlan cpu and memory subsystem the BCM43903 wlan section includes an integrated 32-bit arm cortex-r4 processor with internal ram and rom. the arm cortex-r4 is a low-power processor that features a low gate count, a small interrupt latency, and low-cost debug capabilities. it is intended for deeply embedded applications that require fast interrupt response features. delivering more than a 30% performance gain over arm7tdmi, the arm cortex-r4 implements the arm v7-r architecture with support for the thumb-2 instruction set. at 0.19 w/mhz, the cortex-r4 is the most power efficient general-purpose microprocessor available, outperforming 8- and 16-bit devices on mips/w. it also supports integrated sleep modes. on-chip memory for this cpu includes 576 kb of sram and 448 kb of rom. ieee 802.11n mac the BCM43903 wlan media access controller (mac) is designed to support high-throughput operation with low power consumption. it does so without compromising the bluetooth coexistence policies, thereby enabling optimal performance over both networks. in addition, several power-saving modes have been implemented that allow the mac to consume very little power while maintaining network-wide timing synchronization. the architecture diagram of the mac is shown in figure 8 . the following sections provide an overview of the important mac modules. ieee 802.11n mac BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 32 figure 8: wlan mac architecture the BCM43903 wlan mac supports features specified in the ieee 802.11 base standard and amended by ieee 802.11n. the key mac features include: ? transmission and reception of aggregated mpdus (a-mpdu) for high throughput (ht). ? support for power management schemes, including wmm power-save, power-save multi-poll (psmp), and multiphase psmp operation. ? support for immediate ack and block-ack policies. ? interframe space timing support, including rifs. ? support for rts/cts and cts-to-self frame sequences for protecting frame exchanges. ? back-off counters in hardware for supporting multiple priorities as specified in the wmm specification. ? timing synchronization function (tsf), network allocation vector (nav) maintenance, and target beacon transmission time (tbtt) generation in hardware. ? hardware offload for aes-ccmp, legacy wpa tkip, legacy wep ciphers, wapi, and support for key management. ? support for coexistence with bluetooth and other external radios. ? programmable independent basic service set (ibss) or infrastructure basic service set functionality. ? statistics counters for mib support. embedded cpu interface host registers, dma engines tx-fifo 32 kb wep tkip, aes, wapi txe tx a-mpdu rxe pmq psm shared memory 6 kb psm ucode memory ext- ihr ifs backoff, btcx tsf nav ihr bus shm bus mac-phy interface rx-fifo 10 kb rx a-mpdu ieee 802.11n mac BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 33 psm the programmable state machine (psm) is a microcoded engine that provides most of the low-level control to the hardware in order to implement the ieee 802.11 specification. it is a microcontroller that is highly optimized for flow-control operations, which are predominant in implementations of communication protocols. the instruction set and fundamental operations are simple and general, allowing algorithms to be optimized very late in the design process. it also allows for changes to the algorithms to track evolving ieee 802.11 specifications. the psm fetches instructions from microcode memory. it uses the shared memory to obtain operands for instructions, as a data store, and to exchange data between both the host and the mac data pipeline (via the shm bus). the psm also uses a scratch-pad memory (similar to a register bank) to store frequently accessed and temporary variables. the psm exercises fine-grained control over the hardware engines by programming internal hardware registers (ihr). these ihrs are colocated with the hardware functions they control and are accessed by the psm via the ihr bus. the psm fetches instructions from the microcode memory using an address determined by the program counter, instruction literal, or a program stack. for alu operations, the operands are obtained from shared memory, scratch-pad memory, ihrs, or instruction literals, and the results are written into the shared memory, scratch-pad memory, or ihrs. there are two basic branch instructions: conditional branches and alu-based branches. to better support the many decision points in the ieee 802.11 algorithms, branches can depend on either readily available signals from the hardware modules (branch condition signals are available to the psm without polling the ihrs) or on the results of alu operations. wep the wired equivalent privacy (wep) engine encapsulates all the hardware accelerators to perform encryption and decryption as well as mic computation and verification. the accelerators implement the following cipher algorithms: legacy wep, wpa tkip, wpa2 aes-ccmp. the psm determines, based on the frame type and association information, the appropriate cipher algorithm to use. it supplies the keys to the hardware engines from an on-chip key table. the wep interfaces with the transmit engine (txe) to encrypt and compute the mic on transmit frames and the receive engine (rxe) to decrypt and verify the mic on receive frames. ieee 802.11n mac BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 34 txe the transmit engine (txe) constitutes the transmit data path of the mac. it coordinates the dma engines to store the transmit frames in the txfifo. it interfaces with the wep module to encrypt frames and transfers the frames across the mac-phy interface at the appropriate time determined by the channel-access mechanisms. the data received from the dma engines are stored in transmit fifos. the mac has multiple logical queues to support traffic streams that have different qos priority requirements. the psm uses the channel access information from the ifs module to schedule a queue from which the next frame is transmitted. once the frame is scheduled, the txe hardware transmits the frame based on a precise timing trigger received from the ifs module. the txe module also contains the hardware that allows the rapid assembly of mpdus into an a-mpdu for transmission. the hardware module aggregates the encrypted mpdus by adding appropriate headers and pad delimiters as needed. rxe the receive engine (rxe) constitutes the receive data path of the mac. it interfaces with the dma engine to drain the received frames from the rxfifo. it transfers bytes across the mac-phy interface and interfaces with the wep module to decrypt frames. the decrypted data is stored in the rxfifo. the rxe module contains filters that are programmed by the psm to accept or filter frames based on several criteria such as receiver address, bssid, and certain frame types. the rxe module also contains the hardware required to detect a-mpdus, parse the headers of the containers, and disaggregate them into component mpdus. ifs the ifs module contains the timers required to determine interframe-space timing including rifs timing. it also contains multiple backoff engines required to support prioritized access to the medium as specified by wmm. the interframe-spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the phy. these timers provide precise timing to the txe to begin frame transmission. the txe uses this information to send response frames or perform transmit frame-bursting (rifs or sifs separated, as within a txop). the backoff engines (for each access category) monitor channel activity, in each slot duration, to determine whether to continue or pause the backoff counters. when the backoff counters reach 0, the txe gets notified so that it may commence frame transmission. in the event of multiple backoff counters decrementing to 0 at the same time, the hardware resolves the conflict based on policies provided by the psm. the ifs module also incorporates hardware that allows the mac to enter a low-power state when operating under the ieee power save mode. in this mode, the mac is in a suspended state with its clock turned off. a sleep timer, whose count value is initialized by the psm, runs on a slow clock and determines the duration over which the mac remains in this suspended state. when the timer expires, the mac is restored to its functional state. the psm updates the tsf timer based on the sleep duration, ensuring that the tsf is synchronized to the network. ieee 802.11n mac BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 35 the ifs module also contains the pta hardware that assists the psm in bluetooth coexistence functions. tsf the timing synchronization function (tsf) module maintains the tsf timer of the mac. it also maintains the target beacon transmission time (tbtt). the tsf timer hardware, under the control of the psm, is capable of adopting timestamps received from beacon and probe response frames in order to maintain synchronization with the network. the tsf module also generates trigger signals for events that are specified as offsets from the tsf timer, such as uplink and downlink transmission times used in psmp. nav the network allocation vector (nav) timer module is responsible for maintaining the nav information conveyed through the duration field of mac frames. this ensures that the mac complies with the protection mechanisms specified in the standard. the hardware, under the control of the psm, maintains the nav timer and updates the timer appropriately based on received frames. this timing information is provided to the ifs module, which uses it as a virtual carrier- sense indication. mac-phy interface the mac-phy interface consists of a data path interface to exchange rx/tx data from/to the phy. in addition, there is an programming interface that can be controlled either by the host or the psm to configure and control the phy. ieee 802.11 ? b/g/n phy BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 36 ieee 802.11 ? b/g/n phy the BCM43903 wlan digital phy complies with ieee 802.11b/g/n single-stream specifications to provide wireless lan connectivity supporting data rates from 1 mbps to 433.3 mbps for low-power, high-performance, handheld applications. the phy has been designed to work in the presence of interference, radio nonlinearity, and various other impairments. it incorporates optimized implementations of filters, ffts, and viterbi-decoder algorithms. efficient algorithms have been designed to achieve maximum throughput and reliability, including algorithms for carrier sensing and rejection, frequency/phase/timing acquisition and tracking, and channel estimation and tracking. the phy receiver also contains a robust ieee 802.11b demodulator. the phy carrier-sensing algorithm provides high throughput for ieee 802.11b/g hybrid networks with bluetooth coexistence. the key phy features include: ? programmable data rates from mcs0?7 in 20 mhz channels. ? support for optional short gi and green field modes in tx and rx. ? tx and rx ldpc for improved range and power efficiency. ? all scrambling, encoding, forward error correction, and modulation in the transmit direction and inverse operations in the receive direction. ? support for ieee 802.11h/k for worldwide operation. ? advanced algorithms for low power consumption and enhanced sensitivity, range, and reliability. ? algorithms to improve performance in the presence of externally received bluetooth signals. ? an automatic gain control scheme for blocking and nonblocking cellular applications. ? closed loop transmit power control. ? digital rf chip calibration algorithms to handle cmos rf chip process, voltage, and temperature (pvt) variations. ? on-the-fly channel frequency and transmit power selection. ? per-packet rx antenna diversity. ? available per-packet channel quality and signal-strength measurements. ? compliance with fcc and other worldwide regulatory requirements. ieee 802.11 ? b/g/n phy BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 37 figure 9: wlan phy block diagram filters and radio comp frequency and timing synch carrier sense, agc, and rx fsm radio control block common logic block filters and radio comp afe and radio mac interface buffers ofdm demodulate viterbi decoder tx fsm pa comp modulation and coding frame and scramble fft/ifft cck/dsss demodulate descramble and deframe coex modulate/ spread wlan radio subsystem BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 38 section 8: wlan radio subsystem the BCM43903 includes an integrated wlan rf transceiver that has been optimized for use in 2.4 ghz wireless lan systems. it has been designed to provide low-power, low-cost, and robust communications for applications operating in the globally available 2.4 ghz unlicensed ism band. the transmit and receive sections include all on-chip filtering, mixing, and gain control functions. ten rf control signals are available to drive external rf switches. see the reference board schematics for more information. a block diagram of the radio subsystem is shown in figure 10 on page 39 . note that integrated on-chip baluns (not shown) convert the fully differential transmit and receive paths to single-ended signal pins. receiver path the BCM43903 has a wide dynamic range, direct conversion receiver that employs high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 ghz ism band. the 2.4 ghz path has a dedicated on-chip low-noise amplifier (lna). transmit path baseband data is modulated and upconverted to the 2.4 ghz ism band. linear on-chip power amplifiers deliver high output powers while meeting ieee 802.11b/g/n specifications without the need for external pas. when using the internal pa, which is required in the 2.4 ghz band, closed-loop output power control is completely integrated. calibration the BCM43903 features dynamic and automatic on-chip calibration to continually compensate for temperature and process variations across components. these calibration routines are performed periodically during the course of normal radio operation. examples of some of the automatic calibration algorithms are baseband filter calibration for optimum transmit and receive performance and loft calibration for carrier leakage reduction. in addition, i/q calibration and vco calibration are performed on-chip. no per-board calibration is required during manufacturing testing. this helps to minimize the test time and cost in large-volume production environments. calibration BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 39 figure 10: radio functional block diagram wl logen wl pll wlan bb voltage regulators lpo/ext lpo/rcal wl adc wl pa wl tx 2.4 ghz mixer wl dac wl txlpf wl rxlpf wl rx 2.4 ghz mixer wl-g-lna11 wl g-lna12 shared xo wl txlpf wl dac wl adc wl rxlpf wl 2.4 ghz rx wl 2.4 ghz tx tx mode switch tx mode switch xop xon broadcom ? march 12, 2016 ? 43903-ds102-r page 40 pinout and signal descriptions broadcom confidential BCM43903 preliminary data sheet section 9: pinout and signal descriptions ball map figure 11: 151-ball wlbga map?top view with balls facing down pnmlkjhgfedcba 12 vddio rf_sw_ ctrl_8 rf_sw_ ctrl_7 pwr_gnd nc_j12 nc_h12 gpio_3 gpio_6 vout_3p3 ldo_ vddbat5v ldo_ vdd1p5 sr_ vddbat5v sr_pvss 12 11 srstn rf_sw_ ctrl_9 vssc rf_sw_ ctrl_1 vssc nc_j11 vddc nc_g11 gpio_5 vddio vout_lnldo vout_ hsicldo vout_cldo sr_vlx 11 10 jtag_sel nc_n10 rf_sw_ ctrl_5 vddc rf_sw_ ctrl_6 nc_j10 vssc gpio_2 gpio_4 vddio vssc pmu_avss vout_ cldo_sense wl_reg_on 10 9 rf_sw_ ctrl_2 rf_sw_ ctrl_3 rf_sw_ ctrl_0 rf_sw_ ctrl_4 vddio_rf vssc nc_h9 vssc vssc vddio gpio_8 vssc i2c0_sdata vddc 9 8 otp_vdd3p3 avdd1p2 lpo_xtal_in vssc vddio_rf vddio vssc gpio_13 vssc i2c0_clk uart0_txd vddio 8 7 wrf_xtal_ xon wrf_xtal_ gnd1p2 avss vddc vddio vddc vssc vssc uart0_rxd uart0_rts uart0_cts 7 6 wrf_xtal_ xop wrf_xtal_ vdd1p35 wrf_xtal_ vdd1p2 wrf_synth_ vdd3p3 vddc vssc vddc vssc spi0_cs gpio_12 spi0_siso sfl_cs 6 5 wrf_pmu_ vdd1p35 wrf_synth_ vdd1p2 wrf_synth_ gnd wrf_vco_ gnd vddc vssc vddc vddc gpio_7 spi0_miso spi0_clk sfl_clk 5 4 wrf_rx5g_ gnd wrf_afe_ vdd1p35 wrf_general _gnd wrf_ext_ tssia vssc vssc vddc sfl_io3 sfl_io2 sfl_io0 4 3 rf_gnd_p3 wrf_general 2_gnd wrf_afe_ gnd wrf_gpaio_ out hib_reg_ on_in hib_lpo_ selmode hib_wake_b vssc vssc vddc vssc sfl_io1 gpio_14 3 2 rf_gnd_p2 wrf_pa_ gnd3p3 wrf_txmix_ vdd wrf_rx2g_ gnd vssc hib_xtalout hib_xtalin vssc vddc gpio_9 vssc gpio_16 vssc gpio_15 2 1 wrf_pa_ vdd3p3 wrf_ paout_2g wrf_rfin_ 2g vssc vddc hib_reg_on_o ut hib_vddo vddc gpio_0 gpio_1 gpio_10 gpio_11 1 pnmlkjhgfedcba ball list BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 41 ball list ta b l e 6 contains the 151-ball wlbga net names. table 6: wlbga net names ball net name a2 gpio_15 a3 gpio_14 a4 sfl_io0 a5 sfl_clk a6 sfl_cs a7 uart0_cts a8 vddio a9 vddc a10 reg_on a11 sr_vlx a12 sr_pvss b1 gpio_11 b2 vssc b3 sfl_io1 b4 sfl_io2 b5 spi0_clk b6 spi0_siso b7 uart0_rts b8 uart0_txd b9 i2c0_sdata b10 vout_cldo_sense b11 vout_cldo b12 sr_vddbat5v c1 gpio_10 c2 gpio_16 c3 vssc c4 sfl_io3 c5 spi0_miso c6 gpio_12 c7 uart0_rxd c8 i2c0_clk c9 vssc c10 pmu_avss c11 vout_hsicldo c12 ldo_vdd1p5 d1 gpio_1 d2 vssc d3 vddc d4 vddc d7 vssc d8 vssc d9 gpio_8 d10 vssc d11 vout_lnldo d12 ldo_vddbat5v e1 gpio_0 e2 gpio_9 e3 vssc e5 gpio_7 e6 spi0_cs e8 gpio_13 e9 vddio e10 vddio e11 vddio e12 vout_3p3 f1 vddc f2 vddc f5 vddc f6 vssc f8 vssc f9 vssc f10 gpio_4 f11 gpio_5 f12 gpio_6 g1 hib_vddo g2 vssc g3 vssc g4 vssc g6 vddc g7 vssc ball net name ball list BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 42 g9 vssc g10 gpio_2 g11 nc_g11 g12 gpio_3 h1 hib_reg_on_out h2 hib_xtalin h3 hib_wake_b h5 vddc h7 vddc h9 nc_h9 h10 vssc h11 vddc h12 nc_h12 j1 vddc j2 hib_xtalout j3 hib_lpo_selmode j5 vssc j6 vssc j8 vddio j9 vssc j10 nc_j10 j11 nc_j11 j12 nc_j12 k1 vssc k2 vssc k3 hib_reg_on_in k4 vssc k5 vddc k6 vddc k7 vddio k8 vddio_rf k9 vddio_rf k10 rf_sw_ctrl_6 k11 vssc k12 pwr_gnd l1 wrf_rfin_2g l2 wrf_afe_gnd l3 wrf_gpaio_out l4 wrf_ext_tssia l5 wrf_afe_gnd ball net name l6 wrf_synth_vdd3p3 l7 vddc l8 vssc l9 rf_sw_ctrl_4 l10 vddc l11 rf_sw_ctrl_1 l12 rf_sw_ctrl_7 m1 wrf_paout_2g m2 wrf_txmix_vdd m3 wrf_afe_gnd m4 wrf_afe_gnd m5 wrf_afe_gnd m6 wrf_xtal_vdd1p2 m7 avss m8 lpo_xtal_in m9 rf_sw_ctrl_0 m10 rf_sw_ctrl_5 m11 vssc m12 rf_sw_ctrl_8 n2 wrf_afe_gnd n3 wrf_afe_gnd n4 wrf_afe_vdd1p35 n5 wrf_synth_vdd1p2 n6 wrf_xtal_vdd1p35 n7 wrf_afe_gnd n8 avdd1p2 n9 rf_sw_ctrl_3 n10 nc_n10 n11 rf_sw_ctrl_9 n12 vddio p1 wrf_pa_vdd3p3 p2 rf_gnd_p2 p3 rf_gnd_p3 p4 wrf_afe_gnd p5 wrf_pmu_vdd1p35 p6 wrf_xtal_xop p7 wrf_xtal_xon p8 otp_vdd3p3 p9 rf_sw_ctrl_2 p10 jtag_sel ball net name ball list BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 43 p11 srstn ball net name signal descriptions BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 44 signal descriptions ta b l e 7 provides the signal name, type, and description for each BCM43903 ball. the symbols shown under type indicate pin directions (i/o = bidirectional, i = input, and o = output) and the internal pull-up/pull-down characteristics (pu = weak internal pull-up resistor and pd = weak internal pull-down resistor), if any. table 7: signal descriptions ball number signal name type description broadcom serial control (bsc) interfaces c8 i2c0_clk o bsc master clock. b9 i2c0_sdata i/o bsc serial data clocks p6 wrf_xtal_xop i xtal oscillator input. p7 wrf_xtal_xon o xtal oscillator output. m8 lpo_xtal_in i external sleep clock input (32.768 khz). h2 hib_xtalin i 3.3v 32 khz crystal input j2 hib_xtalout o 3.3v 32 khz crystal output gpio interface (wlan) e1 gpio_0 i/o programmable gpio pins. d1 gpio_1 i/o g10 gpio_2 i/o g12 gpio_3 i/o f10 gpio_4 i/o f11 gpio_5 i/o f12 gpio_6 i/o e5 gpio_7 i/o d9 gpio_8 i/o e2 gpio_9 i/o c1 gpio_10 i/o b1 gpio_11 i/o c6 gpio_12 i/o e8 gpio_13 i/o a3 gpio_14 i/o a2 gpio_15 i/o c2 gpio_16 i/o signal descriptions BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 45 ground l2, l5, m3, m4, m5, n2, n3, n7, p4 wrf_afe_gnd gnd afe ground m11, k11, h10, d10, j9, g9, f9, c9, l8, f8, d8, g7, d7, j6, f6, j5, k4, g4, g3, e3, c3, k2, g2, d2, b2, k1 vssc gnd core ground for wlan and app sections a12 sr_pvss gnd power ground c10 pmu_avss gnd quiet ground m7 avss gnd baseband pll ground hibernation block, power-down/power-up, and reset a10 reg_on i used by pmu to power up or power down the internal BCM43903 regulators used by the wlan and app sections. also, when deasserted, this pin holds the wlan and app sections in reset. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. k3 hib_reg_on_in i used by the hibernation block to power up or power down the internal BCM43903 regulators. for applications that use the hibernation block, hib_reg_on_out must connect to reg_on. also, when deasserted, this pin holds the wlan and app sections in reset. h1 hib_reg_on_out o reg_on output signal generated by the hibernation block. h3 hib_wake_b i wake up chip from hibernation mode. j3 hib_lpo_selmode i select precise or coarse 32 khz clock. p11 srstn i system reset. this active-low signal resets the backplanes. jtag interface p10 jtag_sel i jtag select. this pin must be connected to ground if the jtag interface is not used. no connects j10, j11, j12, h9, h12, g11, n10, l4 nc_j10, nc_j11, nc_j12, nc_h9, nc_h12, nc_g11, nc_n10, wrf_ext_tssia ? no connect table 7: signal descriptions (cont.) ball number signal name type description signal descriptions BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 46 power supplies (miscellaneous) p8 otp_vdd3p3 pwr otp 3.3v supply h11, l10, a9, l7, h7, k6, g6, k5, h5, f5, d4, d3, f2, j1, f1 vddc pwr 1.2v core supply for wlan n12, e11, e10, e9, j8, a8, k7 vddio pwr i/o supply k8, k9 vddio_rf pwr i/o supply for rf switch control pads (3.3v). k12 pwr_gnd gnd power supply ground g1 hib_vddo pwr i/o supply for hibernation block n8 avdd1p2 pwr 1.2v supply for baseband pll power supplies (wlan) l6 wrf_synth_vdd3p3 pwr synthesizer vdd 3.3v supply p1 wrf_pa_vdd3p3 pwr 2.4 ghz pa 3.3v vbat supply p5 wrf_pmu_vdd1p35 pwr pmu 1.35v supply m2 wrf_txmix_vdd pwr 3.3v supply for tx mixer n5 wrf_synth_vdd1p2 pwr 1.2v supply for synthesizer n4 wrf_afe_vdd1p35 pwr 1.35v supply for the analog front end (afe) pwm interface (alternate function for gpios) ? pwm0 o pulse width modulation bit 0. ? pwm1 o pulse width modulation bit 1 ? pwm2 o pulse width modulation bit 2 ? pwm3 o pulse width modulation bit 3 ? pwm4 o pulse width modulation bit 4 ? pwm5 o pulse width modulation bit 5 table 7: signal descriptions (cont.) ball number signal name type description signal descriptions BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 47 rf signal interface (wlan) l1 wrf_rfin_2g i 2.4 ghz wlan receiver input p3 rf_gnd_p3 gnd rf ground m1 wrf_paout_2g o 2.4 ghz wlan pa output p2 rf_gnd_p2 gnd rf ground l3 wrf_gpaio_out i/o analog gpio rf switch control lines m9 rf_sw_ctrl_0 o programmable rf switch control lines. the control lines are programmable via the driver and nvram.txt file. l11 rf_sw_ctrl_1 o p9 rf_sw_ctrl_2 o n9 rf_sw_ctrl_3 o l9 rf_sw_ctrl_4 o m10 rf_sw_ctrl_5 i/o k10 rf_sw_ctrl_6 i/o l12 rf_sw_ctrl_7 i/o m12 rf_sw_ctrl_8 i/o n11 rf_sw_ctrl_9 i/o spi flash interface a5 sfl_clk o flash clock a4 sfl_io0 i/o flash data b3 sfl_io1 i/o flash data b4 sfl_io2 i/o flash data c4 sfl_io3 i/o flash data a6 sfl_cs o flash slave select table 7: signal descriptions (cont.) ball number signal name type description signal descriptions BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 48 spi interface note: the spi interface can alternatively be configured and used as a bsc interface. b5 spi0_clk o spi clock c5 spi0_miso i spi data master in b6 spi0_siso o spi data master out e6 spi0_cs o spi slave select uart interface a7 uart0_cts i uart clear-to-send b7 uart0_rts o uart request-to-send c7 uart0_rxd i uart serial input b8 uart0_txd o uart serial output voltage regulators (integrated) b12 sr_vddbat5v i vbat. a11 sr_vlx o cbuck switching regulator output c12 ldo_vdd1p5 i lnldo input d12 ldo_vddbat5v i ldo vbat n6 wrf_xtal_vdd1p35 i xtal ldo input (1.35v) m6 wrf_xtal_vdd1p2 o xtal ldo output (1.2v) d11 vout_lnldo o terminate with 2.2 f capacitor to gnd b11 vout_cldo o output of core ldo e12 vout_3p3 o ldo 3.3v output b10 vout_cldo_sense o voltage sense pin for core ldo c11 vout_hsicldo o output of hsic ldo table 7: signal descriptions (cont.) ball number signal name type description gpio signals and strapping options BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 49 section 10: gpio signals and strapping options overview this section describes gpio signals and strapping options. the pins are sampled at power-on reset (por) to determine various operating modes. sampling occurs a few milliseconds after an internal por or deassertion of the external por. after the por, each pin assumes the gpio or alternative function specified in ta b l e 9 o n page 51 . each strapping option pin has an internal pull-up (pu) or pull-down (pd) resistor that determines the default mode. to change the mode, connect an external pu resistor to vddio or a pd resistor to ground, using a 10 k ? resistor or less. weak pull-down and pull-up resistances at vddo = 3.3v 10%, the minimum, typical, and maximum weak pull-down resistances (for a pin voltage of vddo) are 37.99 k ? , 44.57 k ? , and 51.56 k ? , respectively. at vddo = 3.3v 10%, the minimum, typical, and maximum weak pull-up resistances (for a pin voltage of 0v) are 34.73 k ? , 39.58 k ? , and 44.51 k ? , respectively. note: refer to the reference board schematics for more information. broadcom ? march 12, 2016 ? 43903-ds102-r page 50 strapping options broadcom confidential BCM43903 preliminary data sheet strapping options ta b l e 8 provides the strapping options. table 8: strapping options pin name strap # default internal pull during strap description gpio_1 gspi_mode d1 pd enable gspi interface gpio_7 wcpu_boot_mode e5 pd boot from soc srom or soc sram gpio_11 acpu_boot_mode b1 pd boot from tightly coupled memory (tcm) rom or tcm ram gpio_13 sdio_mode e8 pd select either sdio host mode or sdio device mode gpio_15 vtrim_en a2 pd enable pmu voltage trimming rf_sw_ctrl_5 dap_clk_sel m10 pd select xtal clock or the test clock (tck) for the debug access port (dap) rf_sw_ctrl_7 rsrc_init_mode l12 pd pmu resource initialization mode selection broadcom ? march 12, 2016 ? 43903-ds102-r page 51 alternate gpio signal functions broadcom confidential BCM43903 preliminary data sheet alternate gpio signal functions ta b l e 9 provides the alternate signal functions of the gpio signals. table 9: alternate gpio signal functions gpio default jtag_sel default pull hold/pdlow/pdhigh strap comments gpio_0 ? ? no pull hold ? 8 ma gpio_1 ? ? down hold gspi_mode 8 ma gpio_2 gci_gpio(0) jtag_tck no pull hold ? 8 ma gpio_3 gci_gpio(1) jtag_tms no pull hold ? 8 ma gpio_4 gci_gpio(2) jtag_tdi no pull hold ? 8 ma gpio_5 gci_gpio(3) jtag_tdo no pull hold ? 8 ma gpio_6 gci_gpio(4) jtag_trst no pull hold ? 8 ma gpio_7 ? ? down hold wcpu_boot_mode 8 ma gpio_8 gpio_8 ? no pull hold ? 8 ma gpio_9 gpio_9 ? down hold 8 ma gpio_10 gpio_10 ? no pull hold ? 8 ma gpio_11 ? ? down hold acpu_boot_mode 8 ma gpio_12 gpio_12 ? no pull hold ? 8 ma gpio_13 ? ? down hold sdio_mode 8 ma gpio_14 gpio_14 ? no pull hold ? 8 ma gpio_15 ? ? down hold vtrim_en 8 ma gpio_16 ? ? no pull hold ? 8 ma broadcom ? march 12, 2016 ? 43903-ds102-r page 52 pin multiplexing broadcom confidential BCM43903 preliminary data sheet section 11: pin multiplexing ta b l e 1 0 shows the pin multiplexing functions. table 10: pin multiplexing pin function 1 2 3 4 5 6 7 8 9 10 11 gpio_0 gpio_0 uart0_rxd i2c1_sdata pwm0 spi1_miso pwm2 gpio_12 gpio_8 ? pwm4 ? gpio_1 gpio_1 uart0_txd i2c1_clk pwm1 spi1_clk pwm3 gpio_13 gpio_9 ? pwm5 ? gpio_2 gpio_2 ? ? gci_gpio_0 ? ? ? ? tck ? ? gpio_3 gpio_3 ? ? gci_gpio_1 ? ? ? ? tms ? ? gpio_4 gpio_4 ? ? gci_gpio_2 ? ? ? ? tdi ? ? gpio_5 gpio_5 ? ? gci_gpio_3 ? ? ? ? tdo ? ? gpio_6 gpio_6 ? ? gci_gpio_4 ? ? ? ? trst_l ? ? gpio_7 gpio_7 uart0_ rts_out pwm1 pwm3 spi1_cs i2c1_clk gpio_15 gpio_11 pmu_test_ o ?pwm5 gpio_8 gpio_8 spi1_miso pwm2 pwm4 uart0_rxd ? gpio_16 gpio_12 tap_sel_p i2c1_sdata pwm0 gpio_9 gpio_9 spi1_clk pwm3 pwm5 uart0_txd ? gpio_0 gpio_13 ? i2c1_clk pwm1 gpio_10 gpio_10 spi1_mosi pwm4 i2c1_sdata uart0_ cts_in pwm0 gpio_1 gpio_14 pwm2 ? ? gpio_11 gpio_11 spi1_cs pwm5 i2c1_clk uart0_ rts_out pwm1 gpio_7 gpio_15 pwm3 ? ? gpio_12 gpio_12 i2c1_sdata uart0_rxd spi1_miso pwm2 pwm4 gpio_8 gpio_16 pwm0 ? ? gpio_13 gpio_13 i2c1_clk uart0_txd spi1_clk pwm3 pwm5 gpio_9 gpio_0 pwm1 ? ? gpio_14 gpio_14 pwm0 uart0_ cts_in spi1_mosi i2c1_sdata ? gpio_10 ? pwm4 ? pwm2 gpio_15 gpio_15 pwm1 uart0_ rts_out spi1_cs i2c1_clk ? gpio_11 gpio_7 pwm5 ? pwm3 gpio_16 gpio_16 uart0_ cts_in pwm0 pwm2 spi1_mosi i2c1_sdata gpio_14 gpio_10 rf_ disable_l ?pwm4 rf_sw_ ctrl_5 rf_sw_ ctrl_5 gci_gpio_5????????? rf_sw_ ctrl_6 rf_sw_ ctrl_6 uart_ dbg_rx seci_in???????? broadcom ? march 12, 2016 ? 43903-ds102-r page 53 pin multiplexing broadcom confidential BCM43903 preliminary data sheet rf_sw_ ctrl_7 rf_sw_ ctrl_7 uart_ dbg_tx seci_out???????? rf_sw_ ctrl_8 rf_sw_ ctrl_8 seci_in uart_ dbg_rx ???????? rf_sw_ ctrl_9 rf_sw_ ctrl_9 seci_out uart_ dbg_tx ???????? spi0_miso spi0_miso gpio_17 gpio_24 ? ? ? ? ? ? ? ? spi0_clk spi0_clk gpio_18 gpio_25 ? ? ? ? ? ? ? ? spi0_mosi spi0_mosi gpio_19 gpio_26 ? ? ? ? ? ? ? ? spi0_cs spi0_cs gpio_20 gpio_27 ? ? ? ? ? ? ? ? i2c0_sdata i2c0_sdata gpio_21 gpio_28 ? ? ? ? ? ? ? ? i2c0_clk i2c0_clk gpio_22 gpio_29 ? ? ? ? ? ? ? ? table 10: pin multiplexing pin function 1 2 3 4 5 6 7 8 9 10 11 broadcom ? march 12, 2016 ? 43903-ds102-r page 54 i/o states broadcom confidential BCM43903 preliminary data sheet section 12: i/o states ta b l e 11 provides i/o state information for the signals listed. the following notations are used in table 11 : ? i: input signal ? o: output signal ? i/o: input/output signal ?pu = pulled up ? pd = pulled down ? nopull = neither pulled up nor pulled down table 11: i/o states ball name i/o keeper a active mode low power state/sleep (all power present) power-down b (reg_on held low) out-of-reset; before software download (reg_on high) power rail hib_reg_on_in i n input; pd (pull-down can be disabled.) input; pd (pull-down can be disabled.) input input ? reg_on i n input; pd (pull-down can be disabled.) input; pd (pull-down can be disabled.) input; pd (of 200 k ? ) input; pd (of 200 k ? )? gpio_0 i/o y input/output; pu, pd, or nopull (programmable [default: pd]) input/output; pu, pd, or nopull (programmable [default: pd]) high-z, nopull input; pd vddio gpio_1 i/o y input/output; pu, pd, or nopull (programmable [default: nopull]) input/output; pu, pd, or nopull (programmable [default: nopull]) high-z, nopull input; nopull vddio gpio_2 i/o y input/output; pu, pd, or nopull (programmable [default: nopull]) input/output; pu, pd, or nopull (programmable [default: nopull]) high-z, nopull input; nopull vddio gpio_3 i/o y input/output; pu, pd, or nopull (programmable [default: pd]) input/output; pu, pd, or nopull (programmable [default: pd]) high-z, nopull input; pd vddio broadcom ? march 12, 2016 ? 43903-ds102-r page 55 i/o states broadcom confidential BCM43903 preliminary data sheet gpio_4 i/o y input/output; pu, pd, or nopull (programmable [default: nopull]) input/output; pu, pd, or nopull (programmable [default: nopull]) high-z, nopull input; nopull vddio gpio_5 i/o y input/output; pu, pd, or nopull (programmable [default: pd]) input/output; pu, pd, or nopull (programmable [default: pd]) high-z, nopull input; pd vddio gpio_6 i/o y input/output; pu, pd, or nopull (programmable [default: nopull]) input/output; pu, pd, or nopull (programmable [default: nopull]) high-z, nopull input; nopull vddio gpio_7 i/o y input/output; pu, pd, or nopull (programmable [default: nopull]) input/output; pu, pd, or nopull (programmable [default: nopull]) high-z, nopull input; nopull vddio gpio_8 i/o y input/output; pu, pd, or nopull (programmable [default: pd]) input/output; pu, pd, or nopull (programmable [default: pd]) high-z, nopull input; pd vddio gpio_9 i/o y input/output; pu, pd, or nopull (programmable [default: pd]) input/output; pu, pd, or nopull (programmable [default: pd]) high-z, nopull input; pd vddio gpio_10 i/o y input/output; pu, pd, or nopull (programmable [default: nopull]) input/output; pu, pd, or nopull (programmable [default: nopull]) high-z, nopull input; nopull vddio gpio_11 i/o y input/output; pu, pd, or nopull (programmable [default: pd]) input/output; pu, pd, or nopull (programmable [default: pd]) high-z, nopull input; pd vddio gpio_12 i/o y input/output; pu, pd, or nopull (programmable [default: nopull]) input/output; pu, pd, or nopull (programmable [default: nopull]) high-z, nopull input; nopull vddio gpio_13 i/o y input/output; pu, pd, or nopull (programmable [default: nopull]) input/output; pu, pd, or nopull (programmable [default: nopull]) high-z, nopull input; nopull vddio gpio_14 i/o y input/output; pu, pd, or nopull (programmable [default: nopull]) input/output; pu, pd, or nopull (programmable [default: nopull]) high-z, nopull input; nopull vddio table 11: i/o states ball name i/o keeper a active mode low power state/sleep (all power present) power-down b (reg_on held low) out-of-reset; before software download (reg_on high) power rail broadcom ? march 12, 2016 ? 43903-ds102-r page 56 i/o states broadcom confidential BCM43903 preliminary data sheet gpio_15 i/o y input/output; pu, pd, or nopull (programmable [default: nopull]) input/output; pu, pd, or nopull (programmable [default: nopull]) high-z, nopull input; nopull vddio gpio_16 i/o y input/output; pu, pd, or nopull (programmable [default: nopull]) input/output; pu, pd, or nopull (programmable [default: nopull]) high-z, nopull input; nopull vddio rf_sw_ctrl (0 to 9) i/o y output; nopull output; nopull high-z output; nopull vddio_rf a. keeper column: n = pad has no keeper. y = pad has a keeper. keeper is always active except in power-down state. if there is n o keeper, and it is an input and there is nopull, then the pad should be driven to prevent leakage due to floating pad (wl_reg_on, for example). b. in the power-down state (xx_reg_on=0): high-z; nopull => the pad is disabled because power is not supplied. table 11: i/o states ball name i/o keeper a active mode low power state/sleep (all power present) power-down b (reg_on held low) out-of-reset; before software download (reg_on high) power rail electrical characteristics BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 57 section 13: electrical characteristics absolute maximum ratings note: values in this data sheet are design goals and are subject to change based on the results of device characterization. caution! the absolute maximum ratings in table 12 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. functional operation is not guaranteed under these conditions. operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the device. table 12: absolute maximum ratings parameter symbol value unit dc supply for vbat and pa driver supply a a. for the sr_vddbat5v and ldo_vddbat5v supplies. vbat ?0.5 to +5.5 v dc supply voltage for digital i/o vddio ?0.5 to 3.9 v dc supply voltage for rf switch i/o vddio_rf ?0.5 to 3.9 v dc input supply voltage for cldo, lnldo, and ldo b b. for the ldo_vdd1p5 and wrf_xtal_vdd1p35 supplies. ? ?0.5 to 1.575 v 3.3v dc supply voltage for rf analog c c. for the wrf_synth_vdd3p3, wrf_pa_vdd3p3, and wrf_txmix_vdd supplies. vdd3p3rf ?0.5 to 3.6 v 1.35v dc supply voltage for rf analog d d. for wrf_pmu_vdd1p35 and wrf_afe_vdd1p35 supplies. vdd1p35rf ?0.5 to 1.5 v 1.2v dc supply voltage for rf analog e e. for the wrf_synth_vdd1p2 supply. vdd1p2rf ?0.5 to 1.26 v 1.2v dc supply voltage for analog circuits f f. for the avdd1p2 supply. vdd1p2a ?0.5 to 1.26 v dc supply voltage for the core g g. for the vdd supply. vddc ?0.5 to 1.32 v dc supply voltage for otp memory otp_vdd3p3 ?0.5 to 3.9 v maximum undershoot voltage for i/o v undershoot ?0.5 v maximum junction temperature t j 125 c environmental ratings BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 58 environmental ratings the environmental ratings are shown in table 13 . electrostatic disch arge specifications extreme caution must be exercised to prevent electrostatic discharge (esd) damage. proper use of wrist and heel grounding straps to discharge static electricity is required when handling these devices. always store unused material in its antistatic packaging. table 13: environmental ratings characteristic value units conditions/comments ambient temperature (t a ) ?30 to +85 c functional operation storage temperature ?40 to +125 c ? relative humidity less than 60 % storage less than 85 % operation table 14: esd specifications pin type symbol condition esd rating unit esd, handling reference: nqy00083, section 3.4, group d9, table b esd_hand_hbm human body model contact discharge per jedec eid/jesd22-a114 1.5 k ? v cdm esd_hand_cdm charged device model contact discharge per jedec eia/jesd22-c101 250 v recommended operating conditions and dc characteristics BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 59 recommended operating conditi ons and dc characteristics caution! functional operation is not guaranteed outside of the limits shown in table 15 . operation outside these limits for extended periods can adversely affect long-term reliability of the device. table 15: recommended operating conditions and dc characteristics parameter symbol value unit minimum typical maximum dc supply voltage for vbat vbat 2.3 a 3.6 4.8 v dc supply voltage for digital i/o vddio 1.71 ? 3.63 v dc supply voltage for rf switch i/os vddio_rf b 3.13 3.3 3.6 v dc input supply voltage for cldo, lnldo, and ldo ? 1.3 1.35 1.5 v 3.3v dc supply voltage for rf analog vdd3p3rf c 33.33.45v 1.35v dc supply voltage for rf analog vdd1p35rf c 1.3 1.35 1.5 v 1.2v dc supply voltage for rf analog vdd1p2rf c 1.1 1.2 1.26 v 1.2v dc supply voltage for analog vdd1p2a c 1.1 1.2 1.26 v dc supply voltage for core vddc 1.14 1.2 1.26 v dc supply voltage for otp memory otp_vdd3p3 b 2.97 3.3 3.63 v dc supply voltage for tcxo input buffer wrf_tcxo_vdd c 1.62 1.8 1.98 v internal por threshold vth_por 0.4 ? 0.7 v other digital i/o pins for vddio = 1.8v: input high voltage vih 0.65 vddio ? ?v input low voltage vil ? ? 0.35 vddio v output high voltage @ 2 ma voh vddio ? 0.45 ? ?v output low voltage @ 2 ma vol ? ?0.45v for vddio = 3.3v: input high voltage vih 2.00 ? ?v input low voltage vil ? ?0.80v output high voltage @ 2 ma voh vddio ? 0.4 ? ?v output low voltage @ 2 ma vol ? ?0.40v rf switch control output pins d for vddio_rf = 3.3v: output high voltage @ 2 ma voh vddio ? 0.4 ? ?v output low voltage @ 2 ma vol ? ?0.40v recommended operating conditions and dc characteristics BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 60 input capacitance c in ? ? 5 pf a. the BCM43903 is functional across this range of voltages. optimal rf performance specified in the data sheet, however, is guaranteed only for 3v < vbat < 4.8v. b. vdd3p3rf, which is an internally generated supply, can drive this node. there is sufficient current and the appropriate state is maintained during hibernation and sleep cycles. c. internally generated supply. d. programmable 2 ma to 16 ma drive strength. default is 10 ma. table 15: recommended operating conditions and dc characteristics (cont.) parameter symbol value unit minimum typical maximum power supply segments BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 61 power supply segments the digital i/o's are placed in physical segments. the supply voltage for each segment can be independently selected. ta b l e 1 6 shows the power supply segments and the i/o pins associated with each segment. gpio, uart, and jtag interfaces dc characteristics table 16: power supply segments power supply segment pins vddio gpio_0, gpio_1, gpio_2, gpio_3, gpio_4, gpio_5, gpio_6, gpio_7, gpio_8, gpio_9, gpio_10, gpio_11, gpio_12, gpio_13, gpio_14, gpio_15, gpio_16, i2c0_clk, i2c0_sdata, i2c1_clk, i2c1_sdata, jtag_sel, sfl_clk, sfl_cs, sfl_io0, sfl_io1, sfl_io2, sfl_io3, spi0_clk, spi0_cs, spi0_miso, spi0_siso, spi1_clk, spi1_cs, spi1_miso, spi1_siso, srstn, uart0_cts, uart0_rts, uart0_rxd, uart0_txd vddio_rf rf_sw_ctrl_0, rf_sw_ctr l_1, rf_sw_ctrl_2, rf_sw_ctrl_3, rf_sw_ctrl_4, rf_sw_ctrl_5, rf_sw_ctrl_6, rf_sw_ctrl_7, rf_sw_ctrl_8, rf_sw_ctrl_9 table 17: gpio, uart, and jtag interfaces parameter symbol minimum maximum units conditions logic input high voltage v ih 2.0 vddio + 0.5 v ? logic input low voltage v il ?0.5 0.8 v ? logic output high voltage v oh 2.4 ? v ? logic output low voltage v ol ?0.4v? wlan rf specifications BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 62 section 14: wlan rf specifications introduction the BCM43903 includes an integrated direct conversion radio that supports the 2.4 ghz band. this section describes the rf characteristics of the 2.4 ghz radio. unless otherwise stated, limit values apply for the conditions specified in table 13: ?environmental ratings,? on page 58 and table 15: ?recommended operating conditions and dc characteristics,? on page 59 . typical values apply for the following conditions: ? vbat = 3.6v ? ambient temperature +25c figure 12: port locations for wlan testing 2.4 ghz band genera l rf specifications note: values in this section of the data sheet are design goals and are subject to change based on device characterization results. table 18: 2.4 ghz band general rf specifications item condition minimum typical maximum unit tx/rx switch time including tx ramp down ?? 5 s rx/tx switch time including tx ramp up ? ? 2 s power-up and power-down ramp time dsss/cck modulations ?? < 2s 2.4 ghz wlan tx (wrf_paout_2g) 2.4 ghz wlan rx (wrf_rfin_2g) chip output port chip input port rf port filter BCM43903 wlan 2.4 ghz receiver performance specifications BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 63 wlan 2.4 ghz receiver pe rformance specifications note: the specifications shown in ta b le 1 9 apply at the chip ports, unless otherwise defined. table 19: wlan 2.4 ghz receiver performance specifications parameter condition/notes minimum typical maximum unit frequency range ? 2400 ? 2500 mhz rx sensitivity ieee 802.11b (8% per for 1024 octet psdu) 1 mbps dsss ? ?98.9 ? dbm 2 mbps dsss ? ?96.0 ? dbm 5.5 mbps dsss ? ?93.9 ? dbm 11 mbps dsss ? ?90.4 ? dbm rx sensitivity ieee 802.11g (10% per for 1024 octet psdu) 6 mbps ofdm ? ?95.0 ? dbm 9 mbps ofdm ? ?93.8 ? dbm 12 mbps ofdm ? ?92.7 ? dbm 18 mbps ofdm ? ?90.3 ? dbm 24 mbps ofdm ? ?87.1 ? dbm 36 mbps ofdm ? ?83.6 ? dbm 48 mbps ofdm ? ?79.3 ? dbm 54 mbps ofdm ? ?78.0 ? dbm rx sensitivity ieee 802.11n (10% per for 4096 octet psdu) a defined for default parameters: 800 ns gi and non-stbc. 20 mhz channel spacing for all mcs rates mcs0 ? ?94.6 ? dbm mcs1 ? ?92.1 ? dbm mcs2 ? ?89.8 ? dbm mcs3 ? ?86.6 ? dbm mcs4 ? ?83.0 ? dbm mcs5 ? ?78.3 ? dbm mcs6 ? ?76.6 ? dbm mcs7 ? ?75.0 ? dbm input in-band ip3 maximum lna gain ? ?8 ? dbm minimum lna gain ? +9 ? dbm wlan 2.4 ghz receiver performance specifications BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 64 maximum receive level @ 2.4 ghz @ 1, 2 mbps (8% per, 1024 octets) ?3.5 ? ? dbm @ 5.5, 11 mbps (8% per, 1024 octets) ?9.5 ? ? dbm @ 6, 9, 12 mbps (10% per, 1024 octets) ?9.5 ? ? dbm @ mcs0?2 rates (10% per, 4095 octets) ?9.5 ? ? dbm @ 18, 24, 36, 48, 54 mbps (10% per, 1024 octets) ?14.5 ? ? dbm @ mcs3?7 rates (10% per, 4095 octets) ?14.5 ? ? dbm adjacent channel rejection- dsss (difference between interfering and desired signal at 8% per for 1024 octet psdu with desired signal level as specified in condition/notes.) desired and interfering signal 30 mhz apart 1 mbps dsss ?74 dbm 35 ? ? db 2 mbps dsss ?74 dbm 35 ? ? db desired and interfering signal 25 mhz apart 5.5 mbps dsss ?70 dbm 35 ? ? db 11 mbps dsss ?70 dbm 35 ? ? db adjacent channel rejection- ofdm (difference between interfering and desired signal (25 mhz apart) at 10% per for 1024 octet psdu with desired signal level as specified in condition/notes.) 6 mbps ofdm ?79 dbm 16 ? ? db 9 mbps ofdm ?78 dbm 15 ? ? db 12 mbps ofdm ?76 dbm 13 ? ? db 18 mbps ofdm ?74 dbm 11 ? ? db 24 mbps ofdm ?71 dbm 8 ? ? db 36 mbps ofdm ?67 dbm 4 ? ? db 48 mbps ofdm ?63 dbm 0 ? ? db 54 mbps ofdm ?62 dbm ?1 ? ? db adjacent channel rejection mcs0?7 (difference between interfering and desired signal (25 mhz apart) at 10% per for 4096 octet psdu with desired signal level as specified in condition/notes.) mcs0 ?79 dbm 16 ? ? db mcs1 ?76 dbm 13 ? ? db mcs2 ?74 dbm 11 ? ? db mcs3 ?71 dbm 8 ? ? db mcs4 ?67 dbm 4 ? ? db mcs5 ?63 dbm 0 ? ? db mcs6 ?62 dbm ?1 ? ? db mcs7 ?61 dbm ?2 ? ? db maximum receiver gain ? ? ? 66 ? db gain control step ? ? ? 3 ? db rssi accuracy b range ?95 c dbm to ?30 dbm ?5 ? 5 db range above ?30 dbm ?8 ? 8 db return loss z o = 50 ? , across the dynamic range 10 11.5 13 db table 19: wlan 2.4 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit wlan 2.4 ghz receiver performance specifications BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 65 receiver cascaded noise figure at maximum gain ? 4 ? db a. sensitivity degradations for alternate settings in mcs modes. mm: 0.5 db drop, and sgi: 2 db drop. b. the minimum and maximum values shown have a 95% confidence level. c. ?95 dbm with calibration at time of manufacture, ?92 dbm without calibration. table 19: wlan 2.4 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit wlan 2.4 ghz transmitter performance specifications BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 66 wlan 2.4 ghz transmitter performance specifications note: unless otherwise noted, the values shown in ta b le 2 0 apply at the chip ports. table 20: wlan 2.4 ghz transmitter performance specifications parameter condition/notes minimum typical maximum unit frequency range ? 2400 ? 2500 mhz rf port tx power evm a (highest power setting, 25c, and vbat = 3.6) a. this specification row indicates the linear power specification as measured from the chip output port. the requirement is in dbm (tx power). the ratio (db) in the conditions/notes column is the evm. dss/cck ?9 db ? 20.5 ? dbm ofdm, bpsk ?8 db ? 20 ? dbm ofdm, qpsk ?13 db ? 20 ? dbm ofdm, 16-qam ?19 db ? 19 ? dbm ofdm, 64-qam (r = 3/4) ?25 db ? 19 ? dbm ofdm, 64-qam (mcs7, ht20) ?27 db ? 18.5 ? dbm ofdm evm b (25c, vbat = 3.6v) b. this specification row indicates the evm floor. the requirement is in db (evm). the power in the conditions/ notes column is the tx power specification in dbm. ofdm, bpsk 5 dbm ?29 ?31 ? db ofdm, 64-qam 5 dbm ?31 ?33 ? db mcs7 5 dbm ?33 ?35 ? db phase noise 37.4 mhz crystal, integrated from 10 khz to 10 mhz ? 0.45 ? degrees tx power control dynamic range ?10??db closed-loop tx power variation at highest power level setting across full temperature and voltage range. applies to 10 dbm to 20 dbm output power range. ??1.5db carrier suppression ? 15 ? ? dbc gain control step ? ? 0.25 ? db return loss at chip port tx z o = 50 ? ?6?db general spurious emissions specifications BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 67 general spurious emi ssions specifications this section provides the tx and rx spurious emissions specifications for the wlan 2.4 ghz band. the recommended spectrum analyzer settings for the spurious emissions specifications are provided in ta b l e 2 1 . transmitter spurious emissions specifications 2.4 ghz band spurious emissions 20-mhz channel spacing table 21: recommended spectrum analyzer settings parameter setting resolution bandwidth (rbw) 1 mhz video bandwidth (vbw) 1 mhz sweep auto span 100 mhz detector maximum peak trace maximum hold modulation ofdm note: possible afe combinations are as follows. the afe=vco/18 specifications for channel 2442 are listed in ta b l e 2 2 . ?afe=vco/18 ?afe=vco/16 ?afe=vco/8 ?afe=vco/6 general spurious emissions specifications BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 68 receiver spurious emissions specifications table 22: 2.4 ghz band, 20-mhz channel spacing tx spurious emissions specifications a a. vco = 1.5 fch, where fch is the center frequency of the channel. spurious frequency power (dbm) frequency (fch; mhz) channel 2442 typical (dbm) maximum (dbm) hd2 ?5 ?58.7 ?56.6 hd3 ?5 ?71.7 ?68.9 hd4 ?5 ?57.2 ?50.2 vco ?5 ?45.7 ?43.7 vcox2 ?5 ?71.5 ?69.0 vcox3 ?5 ?85.2 ?74.1 afex3 ?5 ? ? afex4 ?5 ? ? afex5 ?5 ? ? afex6 ?5 ?78.4 ?73.5 afex7 ?5 ?77.3 ?76.1 afex8 ?5 ?73.6 ?73.4 afex9 ?5 ?70.9 ?69.9 afex10 ?5 ?81.1 ?78.8 afex11 ?5 ?70.3 ?69.1 afex13 ?5 ?72.0 ?71.0 afex14 ?5 ?76.2 ?73.8 afex15 ?5 ?79.3 ?73.6 afex16 ?5 ?82.5 ?77.9 afex17 ?5 ?85.3 ?77.7 afex19 ?5 ?83.4 ?77.6 afex20 ?5 ?83.9 ?76.5 afex21 ?5 ?78.7 ?74.9 afex22 ?5 ?82.1 ?76.2 afex23 ?5 ?87.1 ?77.6 table 23: 2g general receiver spurious emissions band frequency range typical maximum unit 2g 2.4 ghz < f < 2.5 ghz ?75.5 ?74.1 dbm 3.6 ghz < f < 3.8 ghz ?52.8 ?50.9 dbm internal regulator electrical specifications BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 69 section 15: internal regulator electrical specifications core buck switching regulator note: values in this data sheet are design goals and are subject to change based on device characterization results. note: functional operation is not guaranteed outside of the specification limits provided in this section. table 24: core buck switchi ng regulator (cbuck) specifications specification notes min. typ. max. unit input supply voltage (dc) dc voltage range inclusive of disturbances. 3.0 3.6 4.8 a a. the maximum continuous voltage is 4.8v. voltages up to 6.0v for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. voltages as high as 5.0v for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed. v pwm mode switching frequency ccm, load > 100 ma vbat = 3.6v. ? 4 ? mhz pwm output current ? ? ? 550 ma output current limit ? ? 1400 ? ma output voltage range programmable, 30 mv steps. default = 1.35v. 1.2 1.35 1.5 v pwm output voltage dc accuracy includes load and line regulation. forced pwm mode. ?4 ? 4 % pwm ripple voltage, static measure with 20 mhz bandwidth limit. static load. max. ripple based on vbat = 3.6v, vout = 1.35v, fsw = 4 mhz, 2.2 h inductor with min. effective l > 1.05 h, cap. + board total ? esr < 20 m ? , c out > 1.9 f, esl<200 ph ?720mvpp pwm mode peak efficiency peak efficiency at 200 ma load. 78 86 ? % pfm mode efficiency 10 ma load current. 70 81 ? % start-up time from power down vio already on and steady. time from reg_on rising edge to cldo reaching 1.2v. ? 400 500 s external inductor 0806 size, 2.2 h, dcr = 0.11 ? , acr = 1.18 ? @ 4 mhz. ?2.2?h external output capacitor ceramic, x5r, 0402, esr <30 m ? at 4 mhz, 4.7 f 20%, 6.3v. 2.0 b b. minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 4.7 10 c f external input capacitor for sr_vddbat5v pin, ceramic, x5r, 0603, esr < 30 m ? at 4 mhz, 4.7 f 20%, 6.3v. 0.67 b 4.7 ? f input supply voltage ramp-up time 0 to 4.3v. 40 ? ? s 3.3v ldo (ldo3p3) BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 70 3.3v ldo (ldo3p3) c. total capacitance includes those connected at the far end of the active load. table 25: ldo3p3 specifications specification notes min. typ. max. units input supply voltage, v in min. = v o + 0.2v = 3.5v dropout voltage requirement must be met under maximum load for performance specifications. 3.0 3.6 4.8 a a. the maximum continuous voltage is 4.8v. voltages up to 6.0v for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. voltages as high as 5.0v for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed. v output current ? 0.001 ? 450 ma nominal output voltage, v o default = 3.3v. ? 3.3 ? v dropout voltage at max. load. ? ? 200 mv output voltage dc accuracy includes line/load regulation. ?5 ? +5 % quiescent current no load. ? ? 85 a line regulation v in from (v o + 0.2v) to 4.8v, max. load. ? ? 3.5 mv/v load regulation load from 1 ma to 450 ma. ? ? 0.3 mv/ma psrr v in v o + 0.2v, v o = 3.3v, c o = 4.7 f, max load, 100 hz to 100 khz. 20??db ldo turn-on time chip already powered up. ? 160 250 s external output capacitor, c o ceramic, x5r, 0402, (esr: 5 m ? ?240 m ? ), 10%, 10v. 1.0 b b. minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 4.7 10 f external input capacitor for ldo_vddbat5v pin (shared with band gap) ceramic, x5r, 0402, (esr: 30m ? ?200 m ? ), 10%, 10v. not needed if sharing 4.7 f vbat capacitor with sr_vddbat5v. ?4.7?f cldo BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 71 cldo table 26: cldo specifications specification notes min. typ. max. units input supply voltage, v in min. = 1.2 + 0.15v = 1.35v dropout voltage requirement must be met under maximum load. 1.3 1.35 1.5 v output current ? 0.2 ? 350 ma output voltage, v o programmable in 10 mv steps. default = 1.2.v. 0.95 1.2 1.26 v dropout voltage at max. load. ? ? 150 mv output voltage dc accuracy includes line/load regulation. ?4 ? +4 % quiescent current no load. ? 26 ? a 200 ma load. ? 2.48 ? ma line regulation v in from (v o + 0.15v) to 1.5v, maximum load. ??5mv/v load regulation load from 1 ma to 300 ma. ? 0.02 0.05 mv/ma leakage current power down. ? 10 40 a bypass mode. ? 2 6 a psrr @1 khz, vin 1.35v, c o = 4.7 f. 20 ? db start-up time of pmu vio up and steady. time from the reg_on rising edge to the cldo reaching 1.2v. ??700s ldo turn-on time ldo turn-on time when the rest of the chip is up. ? 140 180 s external output capacitor, c o to t a l e s r : 5 m ? ?240 m ? . 3.76 a a. minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 4.7 ? f external input capacitor only use an external input capacitor at the ldo_vdd1p5 pin if it is not supplied from the cbuck output. ?12.2f lnldo BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 72 lnldo table 27: lnldo specifications specification notes min. typ. max. units input supply voltage, vin min. v in = v o + 0.15v = 1.35v (where v o = 1.2v)dropout voltage requirement must be met under maximum load. 1.3 1.35 1.5 v output current ? 0.1 ? 150 ma output voltage, v o programmable in 25 mv steps. default = 1.2v. 1.1 1.2 1.275 v dropout voltage at maximum load. ? ? 150 mv output voltage dc accuracy includes line/load regulation. ?4 ? +4 % quiescent current no load. ? 44 ? a max. load. ? 970 990 a line regulation v in from (v o + 0.1v) to 1.5v, 150 ma load. ? ? 5 mv/v load regulation load from 1 ma to 150 ma. ? 0.02 0.05 mv/ma leakage current power-down. ? ? 10 a output noise @30 khz, 60?150 ma load c o = 2.2 f. @100 khz, 60?150 ma load c o = 2.2 f. ? ? 60 35 nv/rt hz nv/rt hz psrr @ 1khz, input > 1.35v, c o = 2.2 f, v o = 1.2v. 20 ? ? db ldo turn-on time ldo turn-on time when the rest of the chip is up. ? 140 180 s external output capacitor, c o total esr (trace/capacitor): 5 m ? ?240 m ? . 0.5 a a. minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 2.2 4.7 f external input capacitor only use an external input capacitor at the ldo_vdd1p5 pin if it is not supplied from the cbuck output. total esr (trace/capacitor): 30 m ? ? 200 m ? . ? 1 2.2 f bbpll ldo BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 73 bbpll ldo table 28: bbpll ldo specifications parameter conditions and comments min. typ. max. units input supply voltage, v in min. v in = v o + 0.15v = 1.35v (for v o = 1.2v). the dropout voltage requirement must be met under maximum load. 1.3 1.35 1.5 v output voltage, v o programmable in 25 mv steps. default = 1.2v. 1.1 1.2 1.275 v dropout voltage at max. load ? ? 150 mv output voltage dc accuracy includes line/load regulation. ?4 ? +4 % output current peak load = 80 ma, average = 35 ma 0.1 ? 55 ma quiescent current no load ? 10 12 a 55 ma load ? 550 570 a line regulation v in from (v o + 0.15v) to 1.5v; 200 ma load ? ? 5 mv/v load regulation load from 1ma to 200 ma; v in (v o + 0.15v) ? 0.025 0.045 mv/ma leakage current powered down. junction temperature is 85c. ? 5 20 a bypass mode ? 0.2 1.5 a psrr @1 khz, v in v o + 0.15v, co = 4.7 f 20 ? ? db start-up time of pmu vio up and steady. time from reg_on rising edge to cldo reaching 99% of v o . ?530700us ldo turn-on time the ldo turn-on time when the rest of the chip is up. ?140180us inrush current vin=vo+0.15v to 1.5v, co=0.47uf, no load ? 60 70 ma external output capacitor, c o ceramic, x5r, size 0201, max. 6.3v, 20% tolerance 0.27 0.47 ? f external input capacitor only use an external input capacitor at the ldo_vdd1p5 pin if it is not supplied from the cbuck output. ?1?f system power consumption BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 74 section 16: system power consumption wlan current consumption the tables in this subsection show the typical, total current used by the BCM43903. current values may be measured with the apps core powered off. the first column of the table, the mode description, will state the power condition of the apps core. 2.4 ghz mode note: values in this data sheet are design goals and are subject to change based on the results of device characterization. note: unless otherwise stated, these values apply for the conditions specified in table 15: ?recommended operating conditions and dc characteristics,? on page 59 . table 29: 2.4 ghz mode wlan current consumption mode v bat = 3.6v a (a) a. typical silicon. vddio = vddio_hib = 3.3v a, b (a) b. vio is specified with all pins idle (not switching) and not driving any loads. sleep modes radio off c c. reg_on is low or the device is in hibernation, and all supplies are present. 33 sleep d, e 6 160 ieee power save, dtim=1, single rx, apps powered down f 2180 160 ieee power save, dtim=3, single rx, apps powered down g 680 160 ieee power save, dtim=9, single rx, apps powered down 233 160 active modes continuous rx mode mcs7, ht20, 1ss, apps powered up h, i 57,200 60 crs-ht20, apps powered up j 55,200 60 continuous tx mode 1 mbps, apps powered up k 336,000 60 continuous tx mode mcs7, ht20, 1ss, 1 tx, apps powered up k 337,900 60 ping modes ping to associated access point k 336,000 60 sleep 6 160 wlan current consumption BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 75 d. reg_on is high. apps domain is powered down. wlan domain is in low-power state retention mode. top level is powered up. e. inter-beacon current. f. beacon interval = 102.4 ms. beacon duration = 1 ms @ 1 mbps. average current over 3 dtim intervals. g. beacon interval = 307.2 ms. beacon duration = 1 ms @ 1 mbps. average current over 3 dtim intervals. h. duty cycle is 100%. carrier sense (cs) detect/packet receive. i. measured using packet engine test mode. j. carrier sense (cca) when no carrier present. k. duty cycle is 100%. broadcom ? march 12, 2016 ? 43903-ds102-r page 76 spi flash characteristics broadcom confidential BCM43903 preliminary data sheet section 17: spi flash characteristics spi flash timing read-register timing figure 13 shows the spi flash extended and quad read-register timing. figure 13: spi flash read-register timing note: regarding figure 13 : all read register commands except read lock register are supported. a read nonvolatile configuration register operation will output data starting from the least significant byte. 0 7 8 9 10 11 12 13 14 15 msb command lsb c extended dq0 dq1 high-z d out d out d out d out d out d out d out d out d out 01 23 msb command lsb c quad dq[3:0] d out d out d out msb lsb lsb msb dont care broadcom ? march 12, 2016 ? 43903-ds102-r page 77 spi flash timing broadcom confidential BCM43903 preliminary data sheet write-register timing figure 14 shows the spi flash extended and quad write-register timing. figure 14: spi flash write-register timing note: regarding figure 14 : 1. all write-register commands except write lock register are supported. 2. the waveform must be extended for each protocol: to 23 for extended and five for quad. 3. a write nonvolatile configuration register operation requires data being sent starting from the least significant byte. 0 7 8 9 10 11 12 13 14 15 msb command lsb c extended dq0 d in d in d in d in d in d in d in d in d in 01 23 msb command lsb c quad dq[3:0] d in d in d in msb lsb lsb msb broadcom ? march 12, 2016 ? 43903-ds102-r page 78 spi flash timing broadcom confidential BCM43903 preliminary data sheet memory fast-read timing figure 15 shows the spi flash extended and quad memory fast-read timing. figure 15: memory fast-read timing note: regarding figure 15 : 1. 24-bit addressing is used, so a[max] = a[23] and a[min] = a[0]. 2. for an extended spi protocol, c x = 7 + (a[max] + 1). 3. for a quad spi protocol, c x = 1 + (a[max] + 1)/4. 07 8c x msb command lsb c extended dq0 dq1 high - z d out d out d out d out d out d out d out d out d out 012c x c quad dq[3:0] msb dont care a[max] a[min] lsb dummy cycles msb command lsb a[max] a[min] dummy cycles d out d out d out msb lsb broadcom ? march 12, 2016 ? 43903-ds102-r page 79 spi flash timing broadcom confidential BCM43903 preliminary data sheet memory-write timing figure 16 shows the spi flash extended and quad memory-write (page program) timing. figure 16: memory-write timing note: regarding figure 16 : 1. for an extended spi protocol, c x = 7 + (a[max] + 1). 2. for a quad spi protocol, c x = 1 + (a[max] + 1)/4. 07 8c x msb command lsb c extended dq0 d in d in d in d in d in d in d in d in d in 012c x c quad dq[3:0] msb a[max] a[min] lsb msb command lsb a[max] a[min] d in d in d in msb lsb spi flash timing BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 80 spi flash parameters the combination of figure 17 and ta b le 3 0 provide the spi flash timing parameters. figure 17: spi flash timing parameters diagram table 30: spi flash timing parameters parameter description minimum maximum units t_dvch data setup time 2 ? ns t_chdx data hold time 3 ? ns t_clqx output hold time 1 ? ns t_clqv output valid time (with a 10 pf load) ? 5 ns clock (c) data in (d in ) (dq1 in serial [extended] mode) (dq[3:0] in quad mode) t_dvch t_chdx data out (d out ) (dq0 in serial [extended] mode) (dq[3:0] in quad mode) t_clqx t_clqv power-up sequence and timing BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 81 section 18: power-up sequence and timing sequencing of reset and regulator control signals the BCM43903 has two signals that allow the host to control power consumption by enabling or disabling the internal regulator blocks. these signals are described below. additionally, diagrams are provided to indicate proper sequencing of the signals for various operational states (see figure 18 and figure 19 on page 82 ). the timing values indicated are minimum required values; longer delays are also acceptable. description of control signals ? reg_on : used by the pmu to power-up the BCM43903. it controls the internal BCM43903 regulators. when this pin is high, the regulators are enabled and the device is out of reset. when this pin is low the regulators are disabled. ? hib_reg_on_in : used by the hibernation (hib) block to power up the internal BCM43903 regulators. if the hib_reg_on_in pin is low, the regulators are disabled. for the hib_reg_on_in pin to work as designed, hib_reg_on_out must be connected to reg_on. note: the BCM43903 has an internal power-on reset (por) circuit. the device will be held in reset for a maximum of 110 ms after vddc and vddio have both passed the por threshold. note: the 10%?90% vbat rise time should not be faster than 40 microseconds. vbat should be up before or at the same time as vddio. vddio should not be present first or be held high before vbat is high. sequencing of reset and regulator control signals BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 82 control signal timing diagrams figure 18: reg_on = high, no hi b_reg_on_out connection to reg_on figure 19: hib_reg_on_in = high, hib_reg_on_out connected to reg_on 32.678 khz sleep clock vbat vddio reg_on hib_reg_on_in ~ 2 sleep cycles 32.678 khz sleep clock vbat vddio hib_reg_on_in ~ 2 sleep cycles thermal information BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 83 section 19: thermal information package thermal characteristics junction temperature estimation and psi jt versus theta jc package thermal characterization parameter psi?j t ( ? jt ) yields a better estimation of actual junction temperature (t j ) versus using the junction-to-case thermal resistance parameter theta?j c ( ? jc ). the reason for this is that ? jc assumes that all the power is dissipated through the top surface of the package case. in actual applications, some of the power is dissipated through the bottom and sides of the package. ? jt takes into account power dissipated through the top, bottom, and sides of the package. the equation for calculating the device junction temperature is: t j = t t + p x ? jt where: ?t j = junction temperature at steady-state condition (c) ?t t = package case top center temperature at steady-state condition (c) ? p = device power dissipation (watts) ? ? jt = package thermal characteristics; no airflow (c/w) environmental characteristics for environmental characteristics data, see table 13: ?environmental ratings,? on page 58 . table 31: package thermal characteristics a a. no heat sink, ta = 70c. this is an estimate based on a 4-layer pcb that conforms to eia/jesd51?7. air velocity is 0 m/s. characteristic wlbga ? ja (c/w) (value in still air) 31.72 ? jb (c/w) 3.95 ? jc (c/w) 2.16 ? jt (c/w) 4.3 ? jb (c/w) 9.28 maximum junction temperature t j (c) 113.9 maximum power dissipation (w) 1.38 mechanical information BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 84 section 20: mechanical information figure 20: wlbga package ordering information BCM43903 preliminary data sheet broadcom confidential broadcom ? march 12, 2016 ? 43903-ds102-r page 85 section 21: ordering information part number package description operating ambient temperature BCM43903kubg 4.91 mm x 5.85 mm, 0.4 mm ball pitch, 151-pin wlbga ? ?30c to +85c broadcom web: www.broadcom.com corporate headquarters: san jose, ca ? 2016 by broadcom. all rights reserved. 43903-ds102-r march 12, 2016 broadcom ? reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. information furnished by broadcom is believed to be accurate and reliable. however, broadcom does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herei n, neither does it convey any license under its patent rights nor the rights of others. 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